Semiconductor device and method of manufacturing the same

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device includes: providing a carrier sheet and a device wafer, the device wafer comprising an SOI substrate, and the SOI substrate comprising a bottom-up lower substrate, An insulating buried layer and a semiconductor layer, the first through-hole plug structure in the device wafer extends through the semiconductor layer and the insulating buried layer to at least contact with the lower substrate; the front side of the device wafer is bonded on the carrier sheet; An opening is opened in the bottom, and the opening exposes at least a surface of the first through-hole plug structure in contact with the underlying substrate; and a second insulating medium layer is filled in the opening, so that the first through-hole plug structure and the underlying substrate are formed insulation between. The present invention can avoid short circuit between the device in the semiconductor layer and the underlying substrate, thereby avoiding failure of the semiconductor device.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] The semiconductor-on-insulator (SOI) structure includes a lower substrate, an insulating buried layer and an upper semiconductor layer. According to the thickness of the upper semiconductor layer on the insulating buried layer, the semiconductor-on-insulator structure is divided into thin film fully depleted structures FD-SOI and FD-SOI. Thick-film partially depleted structure PD-SOI. Among them, compared with PD-SOI structure, FD-SOI structure has outstanding advantages such as good proportional reduction characteristics, near-ideal sub-threshold swing, high transconductance and small floating body effect. Applications such as power consumption analog circuits and digital-analog hybrid circuits have received special attention. [0003] However, in the FD-SOI st...

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Problems solved by technology

[0004] 1) see Figure 1a , the FD-SOI structure includes a lower substrate 11, an insulating buried layer 12, and an upper semiconductor layer 13 from bottom to top, an active region surrounded by a shallow trench isolation structure 133 is formed in the upper semiconductor layer 13, and on the upper semiconductor layer 13 Covered with an insulating dielectric layer 14, a gate structure 141 is formed in the insulating dielectric layer 14, and a source region 131 and a drain region 132 are respectively formed in the active regions on both sides of the gate structure 141. After etching the insulating dielectric layer 14 When forming a via hole (not shown) for filling the via plug structure 15, since the thicknesses of the upper semiconductor layer 13 and the insulating buried layer 12 are too small (for example, the thickness of the upper semiconductor layer 13 is only 5 nm to 20 nm, the insulation The thickness of the buried layer 12 is only 10nm to 50nm), so that the etching cannot be accurately stopped in the upper semiconductor layer 13, and the via holes can easily penetrate the upper semiconductor layer 13 and the insulating buried layer 12 and enter the lower substrate 11, resulting in via holes The plug structure 15 enters the underlying substrate 11;

[0005] 2) see Figure 1b ,Will Figure 1a The shown FD-SOI structure is integrated into the same structure with a conventional non-semiconductor-on-insulator structure (without the upper semiconductor layer 13 and the buried insulating layer 12). Since the upper semiconductor layer 13 is not included in the non-semiconductor-on-insulator structure, it is required extending the via plug structure 15 in the non-semiconductor-on-insulator structure from the insulating dielectric layer 14 to the underlying substrate 11, while the via plug structure 15 in the FD-SOI structure cannot extend into the underlying substrate 11, Then, it leads to the need to stop in different selected layers when etching the via hole; if the via hole in the FD-SOI structure and the non-semiconductor-on-insulator structure are formed at the same time, it will cause the via hole in the FD-SOI structure to penetrate the upper layer The semiconductor layer 13 and the insulating buried layer 12 enter the underlying substrate 11; if the via holes in the FD-SOI structure and the non-semiconductor-on-insulator structure are formed in different steps, the complexity of the process will increase;

[0006] 3) see Figure 1c ,and Figure 1a Compared with the shown FD-SOI structure, in technologies below 22nm, due to size reduction, the via plug structure 15 will respectively pass through the junction of the source region 131 and the shallow trench isolation structure 133 and pass through the drain region 132 and the shallow trench isolation structure 133, resulting in etching to form a through hole, due to the difference in the material of the upper semiconductor layer 13 and the shallow trench isolation structure 133, the etching cannot be accurately stopped in the upper semiconductor layer 13, and Due to the reduced width of the via hole, it is difficult to detect the etching end point, which makes it easier to cause the via plug structure 15 to penetrate into the underlying substrate 11

[0007] exist Figure 1a ~ Figure 1c In the shown structure, since the via plug structure 15 in the FD-SOI structure is connected to the source region 131 and the drain region 132, if the via plug structure 15 passes through the source region 131 and the drain region from the insulating dielectric layer 14 If the electrode region 132 enters the lower substrate 11, it will cause a short circuit between the source region 131 and the drain region 132 and the lower substrate 11, thereby causing the semiconductor device to fail.

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