Data access method, device and equipment and computer readable storage medium

Abstract

The invention discloses a data access method which comprises the following steps: analyzing a received data access request to obtain a to-be-accessed target storage unit; obtaining a target position of the target storage unit on the target bit line; performing opening and closing control on a preset selection switch and a division switch according to the target position to obtain an opening and closing control result; performing data access operation on the target storage unit according to the opening and closing control result, wherein the target bit line comprises a near end which is divided by the division switch and is connected with the sensing amplifier through a first fixed end of the selection switch and a far end which is connected with the near end through the division switch, a movable end of the selection switch is connected with the sensing amplifier, a second fixed end of the selection switch is connected with the far end, and the sensing amplifier is used for sensing the level of the storage unit. According to the invention, the memory time delay is greatly reduced, and the occupied area of a chip is greatly reduced. The invention further discloses a device, equipment and a storage medium, which have corresponding technical effects.

Description

technical field [0001] The present invention relates to the field of storage technology, in particular to a data access method, device, equipment and computer-readable storage medium. Background technique [0002] With the rapid development of computers, the capacity of DRAM (Dynamic Random Access Memory, Dynamic Random Access Memory) continues to increase, but the read delay of memory (usually called memory wall) has not been significantly reduced. Because memory design needs to comprehensively consider factors such as memory capacity and storage price per bit, memory manufacturers usually choose to sacrifice latency to pursue lower prices. Therefore, although there are some low-latency memory research results, most of them are used in applications that require Latency and high-end network equipment that does not care about price. [0003] see figure 1 , figure 2 and image 3 , figure 1 is a structural block diagram of a memory chip, figure 2 is a structural block d...

AI Technical Summary

Problems solved by technology

This method does not substantially reduce the delay, and the memory controller design is more complicated

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