Test method, device and system and computer readable medium

Abstract

The invention discloses a testing method, device and system and a computer readable medium, and relates to the technical field of chips, and the method comprises the steps: testing a to-be-tested chip through a signal pin under the condition that a signal end of the to-be-tested chip is connected with the signal pin; and when the test is completed, triggering the isolation device to execute electrical isolation operation on the signal pin, and under the condition that the chip to be tested is disconnected from the signal pin, controlling the matched test chip to keep a power-on state. Therefore, when the test of the to-be-tested chip is completed, the matched test chip triggers the isolation device to execute electrical isolation operation on the signal pin, so that the signal pin can be electrically isolated, the influence of electric leakage of a test system on the current to-be-tested chip is avoided, and the influence on the time sequence of the test system can also be avoided. Meanwhile, the power failure of the testing chip can be avoided, and the frequent restarting of the testing chip is avoided.

Description

technical field [0001] The present application relates to the field of chip technology, and more particularly, to a testing method, apparatus, system, and computer-readable medium. Background technique [0002] The SLT test of the chip (SLT: system level test, system level test) refers to the test performed after the chip is installed on the system motherboard and after the chip is booted and entered into the operating system. The system level test of the chip is often used in the test process of the chip with complex logic functions and a large number of gate circuits, such as the test of the central processing unit CPU and the graphics processing unit GPU. The industry generally conducts the system-level test of the chip after the FT (final test). FT is the last test before the chip leaves the factory. The test object is for the packaged chip. Generally, the CP (Chip Probing, also known as wafer test) will be packaged after the test, and the FT test will be performed afte...

AI Technical Summary

Problems solved by technology

As chips become more and more complex, the firmware or OS program loading time for chip SLT testing is getting longer and longer

When some chips are tested, the test chip needs to participate in the test to complete the test. Then, after completing the test of a chip, when replacing a new chip to be tested, the test chip needs to be restarted, which will seriously affect the test efficiency. and speed

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