Pseudo quarternary flow-process structure used by 16-bit micro-processor

Abstract

The pseudo-four-stage pipeline structure comprises the pipeline controller, the instruction registers, the decoder, the pipeline registers, ALU, the execute unit (EX), and the memory access / register write. The executing of each instruction is divided into four stages: fetching an instruction, decoding the instruction, executing the instruction and the memory accessing and writing. The two stages pipeline is setup in the processor and each pipeline comprises two clock phases (PH1, PH2). The four stages of each instruction are allocated to the four phases in the two pipelines. Thus, the two stages pipeline realizes the four stages stream of instructions.

Description

technical field [0001] The invention belongs to the technical field of computers, relates to the design and manufacture of a microprocessor, in particular to a method for realizing a pseudo four-stage pipeline structure used by a 16-bit microprocessor. Background technique [0002] In the microprocessor design, the controller is one of the key parts. At present, the microprogram controller, multi-stage pipeline and sequential control technology are mainly used for design. [0003] The disadvantage of microprogram controller technology is that the design is complex, and the technical requirements for designers are very high. It is necessary to use ROM to solidify microprograms, and the processor execution speed is low. It is not suitable for the design of RISC structure processors, and does not conform to the development of modern processor design. trend. [0004] Pipeline technology is a widely popular RISC microprocessor design technology. Generally, 3-5 pipelines are used...

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Problems solved by technology

[0003] The disadvantage of microprogram controller technology is that the design is complex, and the technical requirements for designers are very high. It is necessary to use ROM to solidify microprograms, and the processor execution speed is low. It is not suitable for the design of RISC structure processors, and does not conform to the development of modern processor design. trend

[0004] Pipeline technology is a widely popular RISC microprocessor design technology. Generally, 3-5 pipelines are used (7-level pipelines are also used). The disadvantage is that when the pipeline exceeds 3 levels, the design complexity is very high. The technical requirements are very high, and the processing of data-related conflicts and transfer conflicts takes up a lot of design resources, which is not suitable for the design of small microprocessors. In the design for low-end applications, resource efficiency cannot be fully utilized, which will cause human and financial resources. great waste of

[0005] Sequential control technology divides the control process of the processor into multiple control states, and executes one state in each clock cycle. Its disadvantages are slow execution speed and low resource utilization efficiency. For example, 8031 ​​adopts this technology. When the input clock is At 12MHz, an instruction takes at least 1μs (12 clock cycles) to complete

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