Grouping processor and grouping processor system

A processor system and packet processing technology, applied in transmission systems, digital transmission systems, data exchange networks, etc., to solve the problems that transfer commands cannot be described or executed.

Inactive Publication Date: 2003-03-26
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0073] Therefore, there is a problem that a transfer command of a program spanning a plurality of packet processors 101 can neither be described nor executed.

Method used

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  • Grouping processor and grouping processor system
  • Grouping processor and grouping processor system
  • Grouping processor and grouping processor system

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0131] [1] Embodiment of Packet Processor

[0132] figure 1 An embodiment of a packet processor 100 according to the invention is illustrated. This processor 100 with Figure 13 The difference of the shown prior art processor 101 is that a program execution controller 30 and a command execution unit 40 are used instead of the prior art program start unit 30a and controller 40a.

[0133] In addition, the processor 100 is different from the processor 101 in that the program execution controller 30 receives a received packet length signal 223 from the packet data input unit 60 .

[0134]The combination of basic operations in the program execution controller 30 and the command execution unit 40 is the same as the combination of operations in the program starting unit 30a and the controller 40a. However, the processor 100 is also different from the prior art processor 101 in that the program execution controller 30 can change the number of commands for executing the program acc...

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PUM

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Abstract

In a packet processor and a packet processor system for performing predetermined packet processing for an inputted packet in a packet relaying apparatus or the like, a packet data holder sequentially receives a packet from its head; an execution program holder holds a program in which a processing procedure of the packet is described; and a program execution controller determines a command number of a program to be executed based on a provided packet length and the program, and controls an execution of the program. Also, the program execution controller instructs the program execution controller of at least one of the packet processors at a preceding stage and a following stage of a command acquisition timing and a command acquisition position.

Description

technical field [0001] The present invention relates to a packet processor and a packet processor system, and more particularly to a packet processor and a packet processor system for performing predetermined packet processing on a packet input to a device such as a packet forwarding device. [0002] With the recent development of communication technology, in order to exchange data between computers and various information processing hardware (terminals), a global network system has been established in which private networks such as LAN (Local Area Network) are interconnected . [0003] Communication is performed in this global network system according to various communication protocols for each layer in, for example, the OSI (Open System Interconnection) model. Recently, mainstream communication protocols in one layer corresponding to the transport layer / network layer of the OSI model are the TCP / IP protocol (Transmission Control Protocol / Internet Protocol), respectively. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/70H04L29/02H04L29/06
CPCH04L69/12H04L29/0653H04L49/90H04L29/06081H04L49/9073H04L69/22H04L29/06H04L49/9057H04L9/40
Inventor 阿比留健一鹤冈哲明
Owner FUJITSU LTD
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