Transmission convergence sublayer circuit of receiver for asynchronous transmission and its operation method

Abstract

The present invention relates to a transmission collection sublayer circuit of receiver for asynchronous transmission and its operation method. Said circuit is connected between the buffer and decoder. Said decoder can transfer a data-flow enable signal and a data flow to said circuit, under the enablement of said data flow enable signal said circuit can utilize a data processing management circuit to receive and simultaneously temporarity store array byte data in any signal element, and utilize a signal head error check register to receive said byte data and search signal head. After an idlesignal element identification character is used for validating that said signal element is a non-idle signal element or not, when said signal head is found and said signal element is non-idle, an inverse scrambler is used to obtain effective load data of said signal element.

Description

technical field [0001] The present invention relates to a receiver circuit for asynchronous transmission and its operation method, in particular to a transmission convergence sublayer circuit of the receiver for asynchronous transmission and its operation method. Background technique [0002] In a communication system, data is sent from the transmitting system to the receiving system through the transmission medium. Usually the transmitted data is composed of several layers according to a specific communication protocol, and the receiving system follows this specific communication protocol to process the received data layer by layer. In all communication protocols, the lowest layer is called the physical layer (Physical Layer), and in the asynchronous transfer mode (Asynchronous Transfer Mode), the physical layer is subdivided into two units, which are the physical medium sublayer ( Physical Medium) and Transmission Convergence Sublayer. [0003] The data format processed b...

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Problems solved by technology

[0010] However, the descrambling of the payload in the cell, and the reshaping of the data format from bytes to words or double words (Double Words), which are output to the buffer to wait for the processing of the upper unit, etc., must be increased. post-stage circuit to complete

In this way, to complete the synchronous reception of data, check the header, anti-scrambling and data format reformation, etc., it must be completed by the circuit in Figure 2B and the subsequent circuit, which will make the circuit structure very complicated, and by Figure 2B The circuit and the post-stage circuit process the work to be done step by step, which will increase the time spent on processing.

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