Memory device having low write error rate

Abstract

A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.

Description

[0001]This application claims the benefit of Korean Patent Application No. 10-2019-0045314, filed on Apr. 18, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.BACKGROUND1. Technical Field[0002]The present inventive concept relates to a memory device.2. Description of the Related Art[0003]With speeding-up and low-power consumption of electronic devices, memory devices built in the electronic devices also require high-speed read / write operations and low operating voltages. A random access memory (RAM) may be volatile or non-volatile. A volatile RAM loses information stored in the volatile random access memory each time power is removed, and meanwhile, a non-volatile random access memory may keep the memory contents of the non-volatile random access memory, even when power is removed from the memory.[0004]However, in the case of such a non-volatile random access memory, a success rate and a write error rate (W...

Images