Semiconductor device having low parasitic resistance and small junction leakage characteristic
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Benefits of technology
Problems solved by technology
Method used
Image
Examples
first preferred embodiment
[0028] Referring to FIG. 1, an SOI-FET 100 formed on a SOI substrate 11 is shown. The SOI substrate 11 is formed of a silicon substrate 52 and an insulator 51, which is formed on the silicon substrate 52. The SOI-FET is defined and isolated from other transistors by a field oxide layer 50. The SOI-FET 100 includes a source / drain, a gate electrode 13, a silicon layer 16 acting as a channel region and a side wall 14. The source / drain includes a diffusion layer 15 and a metal silicide layer 17. The diffusion layer 15 is formed by implanting impurities in the silicon layer. The diffusion layer 15 includes a (111) silicon plane at the interface of the metal silicide layer 17.
[0029] The metal suicide layer 17 includes a (111) metal silicide plane at its interface with the diffusion layer 15, when the diffusion layer 15 includes the (111) silicon plane, because the (111) silicon plane has a high grid alignment with the metal silicide layer 17 whose crystallographic structure is a cubic sy...
second preferred embodiment
[0036] The difference between the first and second embodiment is the process of manufacturing the SOI-FET 100 shown in FIG. 1. In the first embodiment, although the thermal treatment is performed twice, the thermal treatment is performed three times in the second embodiment. The details of the manufacturing process in the second embodiment are described below with reference to FIGS. 4A through 4D. In the second embodiment, as a typical example, cobalt is used for forming the metal silicide layer 17.
[0037] Referring to FIG. 4A, the SOI layer 12 having a thickness of 32 nm is formed on the SOI substrate 11 that includes the insulator 52 that is formed on the silicon substrate 51. The SOI layer 12 has the (111) silicon plane as its crystal orientation. After forming the field oxide layer 50 for defining an active area, the gate electrode 13 and the side wall 14 are formed on the SOI layer 12, and then, diffusion layer 15 is formed in the SOI layer 12. Next, a cobalt layer 55 having a ...
third preferred embodiment
[0044] In the third embodiment, a metal silicide layer is formed of cobalt as well as the other embodiments. However, a bulk substrate made of silicon is used in the third embodiment, instead of using the SOI substrate.
[0045] Referring to FIG. 5A, a field oxide layer 32 is formed in a silicon substrate 31 to define an active area X. Then, a gate electrode 33 and a side wall 34 are formed on the silicon substrate 31 in the active area X. Then, after a cobalt layer 80 having a thickness of 7 nm, is formed on the entire surface of the silicon substrate 31, a cobalt silicide (CoSi) layer 31 in a first phase is formed by a first thermal treatment in the silicon substrate 31 with reaction between cobalt and silicon. The first thermal treatment is performed at 550° C. for about 30 seconds.
[0046] Next, referring to FIG. 5B, after an unreacted cobalt layer 80 is removed by using an anmoniacal solution bath, an amorphous layer 43 is formed in the silicon substrate 31 by ion implantation. In...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More