Tracking cache coherency in an extended multiple processor environment

Inactive Publication Date: 2007-04-05
UNISYS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the event a second processor desires to use that same line of cache, the possibility exists for contention.

Method used

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  • Tracking cache coherency in an extended multiple processor environment
  • Tracking cache coherency in an extended multiple processor environment
  • Tracking cache coherency in an extended multiple processor environment

Examples

Experimental program
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Embodiment Construction

Multiprocessor Component Assembly

[0026]FIG. 1 is a block diagram of an exemplary multiple processor component assembly that is included as one of the components of the current invention. The multiprocessor component assembly 100 of FIG. 1 depicts a multiprocessor system component having multiple processor sockets 101, 105, 110, and 115. All of the processor sockets have access to memory 120. The memory 120 may a centralized shared memory or may be a distributed shared memory. Access to the memory 120 by the sockets A-D 101, 105, 110, and 115 depends on whether the memory is centralized or grouped. If centralized, then each socket may have a dedicated connection to memory or the connection may be shared as in a buss configuration. If distributed, each socket may have a memory agent (not shown) and an associated memory block.

[0027] The sockets A-D 101, 105, 110, and 115 may communicate with one another via communication links 130-135. The communication links are arranged such that ...

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PUM

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Abstract

A system for tracking cache coherency in multiprocessor environment includes a first cell having a multiprocessor assembly, a memory, and a coherency director including a first intermediate home agent and a first intermediate cache agent. A second cell is similarly equipped. The two cells may share lines of cache in a controlled manner. Interconnection between the two cells connect the intermediate home agent of one cell to the intermediate cache agent of the second cell. Trackers are present in the agents of the first cell and the second cell. The trackers are responsible for keeping track of cache transactions between cells and queuing up requests for lines of cache so that retry attempts may be made. The trackers thus assist in transactions involving sharing lines of cache, exchanging information and resolving conflicts.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims benefit under 35 U.S.C. § 119(e) of provisional U.S. Pat. Ser. Nos. 60 / 722,092, 60 / 722,317, 60 / 722,623, and 60 / 722,633 all filed on Sep., 30, 2005, the disclosures of which are incorporated herein by reference in their entirely. [0002] The following commonly assigned co-pending applications have some subject matter in common with the current application: [0003] U.S. application Ser. No. 11 / XXX,XXX filed Sep. 29, 2006, entitled “Providing Cache coherency in an Extended Multiple Processor Environment”, attorney docket number TN344, which is incorporated herein by reference in its entirety; [0004] U.S. application Ser. No. 11 / XXX,XXX filed Sep. 29, 2006, entitled “Preemptive Eviction Of Cache Lines From A Directory”, attorney docket number TN426, which is incorporated herein by reference in its entirety; and [0005] U.S. application Ser. No. 11 / XXX,XXX filed Sep. 29, 2006, entitled “Dynamic Presence Vector Scaling in...

Claims

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Application Information

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IPC IPC(8): G06F13/00
CPCG06F12/082G06F12/0822G06F12/0826G06F12/0831G06F2212/1048
InventorCOLLIER, JOSH D.SCHIBINGER, JOSEPH S.CHURCH, CRAIG R.
OwnerUNISYS CORP