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Semiconductor chip and stacked semiconductor package having the same

a semiconductor chip and stacking technology, applied in semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of electrical characteristics deterioration, speed decrease, and difference in operation speed between semiconductor chips comprising stacks, so as to reduce parasitic capacitance

Inactive Publication Date: 2013-06-27
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention relates to a semiconductor chip and a stacked semiconductor package that can reduce parasitic capacitance between through-electrodes and a substrate. This is achieved by using a semiconductor chip with a dielectric layer that has a decreasing dielectric constant, which can be a hollow type dielectric layer with air gaps or a porous dielectric layer with air gaps. The dielectric layer with the decreasing dielectric constant can be formed by a double-layered structure of a hollow type dielectric layer and a porous dielectric layer or a double-layered structure of a hollow type dielectric layer and an air gap-free dielectric layer. The use of this structure can improve the performance of semiconductor chips and stacked semiconductor packages.

Problems solved by technology

However, due to parasitic capacitance between a semiconductor chip and a through-electrode, a signal transfer speed decreases, a difference in operation speed between semiconductor chips comprising a stack increases, and power noise increases causing electrical characteristics to deteriorate.

Method used

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  • Semiconductor chip and stacked semiconductor package having the same
  • Semiconductor chip and stacked semiconductor package having the same
  • Semiconductor chip and stacked semiconductor package having the same

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first embodiment

[0036]FIG. 1 is a cross-sectional view illustrating a semiconductor chip in accordance with the present invention.

[0037]Referring to FIG. 1, a semiconductor chip 10A in accordance with a first embodiment of the present invention includes a substrate 100, through-electrodes 200, and a dielectric layer 300 with a dielectric constant decreasing structure.

[0038]The substrate 100 has a first surface 110, a second surface 120 and a circuit unit 130.

[0039]The first surface 110 faces away from the second surface 120, and the circuit unit 130 is formed on the first surface 110. The circuit unit 130 includes, for example, elements such as transistors, capacitors and resistors, to store and process data.

[0040]The through-electrodes 200 pass through the first surface 110 and the second surface 120 of the substrate 100. Each through-electrode 200 may have a circular sectional shape when viewed from the top. Each through-electrode 200 may also have an elliptical, quadrangular or pentagonal sectio...

second embodiment

[0046]FIG. 2 is a cross-sectional view illustrating a semiconductor chip in accordance with the present invention.

[0047]A semiconductor chip 10B in accordance with a second embodiment of the present invention has a construction in which the form of the dielectric layer 300 with a dielectric constant decreasing structure differs from the form of the dielectric layer 300 of the semiconductor chip 10A of the first embodiment described with reference to FIG. 1. Otherwise, the semiconductor chip in accordance with the second embodiment of the present invention has substantially the same construction as the semiconductor chip 10A in accordance with the first embodiment except for the dielectric layer 300 with a dielectric constant decreasing structure. Therefore, repeated descriptions of the same component parts will be omitted herein, and the same terms and the same reference numerals will be used to refer to the same component parts.

[0048]Referring to FIG. 2, in the present embodiment, ...

third embodiment

[0050]FIG. 3 is a cross-sectional view illustrating a semiconductor chip in accordance with the present invention.

[0051]A semiconductor chip 10C in accordance with a third embodiment of the present invention has a construction in which the structure of the dielectric layer 300 with a dielectric constant decreasing structure differs from the form of the dielectric layer 300 of the semiconductor chip 10A of the first embodiment described above with reference to FIG. 1. Hence, the semiconductor chip in accordance with the third embodiment of the present invention has substantially the same construction as the semiconductor chip 10A in accordance with the first embodiment except for the dielectric layer 300 with a dielectric constant decreasing structure. Therefore, repeated descriptions for the same component parts will be omitted herein, and the same terms and the same reference numerals will be used to refer to the same component parts.

[0052]Referring to FIG. 3, in the present embodi...

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Abstract

A semiconductor chip includes a substrate, through-electrodes passing through the substrate, and a dielectric layer formed between the substrate and the through-electrodes and having a dielectric constant decreasing structure.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority under 35 U.S.C. 119(a) to Korean patent application number 10-2011-140033 filed in the Korean intellectual property office on Dec. 22, 2011, which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor device, and more particularly, to a semiconductor chip and a stacked semiconductor package having the same.[0004]2. Description of the Related Art[0005]Packaging technologies for semiconductor devices have continuously been developed to meet the demand toward miniaturization and high capacity. Recently, various techniques for stacked semiconductor packages have been disclosed in the art to improve miniaturization, capacity and mounting efficiency.[0006]The term “stack”, which is referred to in the semiconductor industry, means to vertically pile at least two semiconductor chips or packages. Th...

Claims

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Application Information

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IPC IPC(8): H01L23/48
CPCH01L2224/48091H01L23/481H01L21/7682H01L2224/16145H01L2224/16225H01L2224/48227H01L2225/06527H01L25/03H01L25/0657H01L2225/06517H01L2225/06513H01L2225/06541H01L23/3128H01L24/05H01L24/06H01L24/13H01L24/14H01L24/16H01L24/32H01L24/48H01L24/73H01L2224/02372H01L2224/0401H01L2224/05009H01L2224/05548H01L2224/05567H01L2224/06181H01L2224/13022H01L2224/131H01L2224/14181H01L2224/16235H01L2224/32145H01L2224/32225H01L2224/73204H01L2224/73265H01L2924/15311H01L2924/00014H01L2924/00012H01L2924/014H01L2924/00H01L2224/05552H01L2224/16146H01L2224/17181H01L2225/0651H01L23/5222H01L23/5226H01L2224/13025H01L2924/181H01L23/53295H01L2224/45099H01L2224/45015H01L2924/207H01L23/12H01L23/48H01L25/105H01L2225/1023H01L2225/1041H01L2225/107
Inventor SON, HO YOUNG
Owner SK HYNIX INC