Connection interface circuit, memory storage device and signal generation method

Abstract

A connection interface circuit, a memory storage device and a signal generation method are disclosed. The connection interface circuit is configured to connect a memory controller to a volatile memory module. The connection interface circuit includes a phase locking circuit, a wire module and a signal interface. The signal interface is coupled between the wire module and the memory controller. The phase locking circuit is configured to receive a first clock signal from the memory controller. The phase locking circuit is further configured to generate a second clock signal according to the first clock signal and a delay feature of the wire module. The wire module is configured to provide a third clock signal to the signal interface according to the second clock signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Taiwan application serial no. 108129899, filed on Aug. 21, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.BACKGROUNDTechnical Field[0002]The disclosure relates to a signal processing technology, and in particular, relates to a connection interface circuit, a memory storage device and a signal generation method.Description of Related Art[0003]In general, a memory controller can access a volatile memory module through a connection interface circuit. However, in order to align a clock signal provided to the volatile memory module by the connection interface circuit with a clock signal of the memory controller itself, normally, a delay caused by transmitting the clock signal in the connection interface circuit can be measured first, and then an delay amount of an output signal can be iteratively adjuste...

AI Technical Summary

Benefits of technology

The patent text describes a new connection interface circuit, memory storage device and signal generation method that can make the memory storage device more efficient. The connection interface circuit receives a clock signal from the memory controller and generates a new clock signal based on the delay of the wire module in the connection interface circuit. This new clock signal is then sent to the signal interface between the connection interface circuit and the memory controller. This results in improved signal alignment between the connection interface circuit and the memory controller, which enhances the overall operational efficiency of the memory storage device.

Problems solved by technology

However, in practice, due to factors like temperature changes and / or process errors, the memory controller often needs to spend more time than expected to adjust the clock signal, thereby reducing an operational efficiency of the memory storage device.

Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present disclosure, or that any reference forms a part of the common general knowledge in the art.

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