Core design of PU-MU-CHL structured computer

A PU-MU-CHL, core design technology, applied in the processor, channel processor and main storage device, the field of internal bus connection technology, can solve the problems of complex software management, low system efficiency, memory conflicts, etc., to achieve program High operating efficiency
CN100492337CInactive Publication Date: 2009-05-27ε§œε’ζ±Ÿ +2
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Patents(China)
Current Assignee / Owner
ε§œε’ζ±Ÿ
Publication Date
2009-05-27
Estimated Expiration
Not applicable Β· inactive patent

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Abstract

The invention relates to a core design of PU-MU-CHL computer, which can solve the bus impact and memory impact, to realize multi-memory and multi-mission parallel computer core structure, wherein the PU-MU-CHL structure arranges the external bus inside, to work the channel CHL as PU, and automatically alternatively connect the MU, to improve the efficiency of computer; the PU-MU-CHL computer arranges the manage mission to the hardware, without using process to operate the programs, and the programs over the number of processors can be switched in the instruction period, to execute the stop program. And the PU-MU-CHL computer has simple structure.
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Description

1. Technical field

[0001] The invention provides a computer core component structure design technology, specifically relates to processors, channel processors and main storage devices, peripherals are connected through an internal bus and so on. 2. Background technology

[0002] Now popular is a computer with a CPU-M structure. The core components of this computer mainly include a central processing unit CPU and a main memory M (memory for short), which are connected by an internal bus to form the main body of a CPU-M structure computer. In order to exchange information with external devices, the CPU-M structure computer also introduces an external bus, and uses a channel processor (referred to as a channel) to complete the task of data transmission between memory and peripherals through the external bus. Computers with this structure have the following major problems:

[0003] (1) Multiprocessors share one memory, and memory conflicts often occur;

[0004] (2) Multiple d...

Claims

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