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Data compression

A data, compressing data technology, applied in the field of data compression, can solve problems such as expensive

Inactive Publication Date: 2009-09-16
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this is very expensive
[0014] Therefore, none of the above four potential solutions is really suitable for coping with the ever-increasing test data volume

Method used

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Examples

Experimental program
Comparison scheme
Effect test

example 1

[0088] v 1 =0XX1Xv 1 merged =0XX1Xv 1 merged = 0X010 3 0X010 00010

[0089] v 2 =XX01Xv 1 merged =0X01Xv 2 merged = 1XXXX 1 0X010 00010

[0090] v 3 =0XXX0v 1 merged =0X010v 3 merged = 0X110 2 0X010 00010

[0091] v 4 =1XXXX v 2 merged = 1XXXX 1XXXX 10101

[0092] v 5 =0XXX0v 3 merged = 0XXX0 0X110 01110

[0093] v 6 =XX11Xv 3 merged = 0X110 0X110 01110

[0094] (a) (b) (c) (d) (e) (f)

[0095] Referring to the above example, (a) represents a sequence of 6 test vectors, while (b) shows the merged test vectors generated when the above algorithm is executed. As shown in (c), the resulting sequence includes 3 merged test vectors. The specified bits in the original sequence of test vectors of (a) can be reconstructed from the sequence of combined test vectors of (c) by repeating each merged vector as many times as shown in (d). The reconstructed vector sequence is shown in (e), where the differences from (a) are emphasized. It can be seen that both s...

example 2

[0100] Pattern 1: v 1 merged = 0X010 3V 4 merged =0X010 2

[0101] v 2 merged = 1XXXX 2 v 5 merged =X1XX1 2

[0102] v 3 merged = 0X110 1V 6 merged =0X010 5

[0103] v 2 merged = 1XXXX 2

[0104] Pattern 2: v 4 merged =0X010 2V 3 merged = 0X110 1

[0105] v 5 merged =X1XX1 2

[0106] v 6 merged = 0XX10 2

[0107] (a) (b)

[0108] Thus, it can be seen that the above procedure for pattern rearrangement is optimal, ie results in the shortest possible sequence of merged test vectors.

[0109] Merging of test vectors and rearrangement of test patterns can be integrated into the ATPG process. Now, fill in the don't care stimulus bits by creating compatible test vectors that can be merged.

[0110] exist Figure 2A and 2B Two possible ATPG processes are shown in . exist Figure 2A In , merge fills are done for each individual test pattern immediately after the pattern has been generated....

example 3

[0115] Port 1, Port 2 Port 1 Port 2 Port 1 Port 2

[0116] v 1 =(0XX,1X) v 11 merged = 0XX v 12 merged =1Xv 11 merged = 0X0 3 v 12 merged = 10 6

[0117] v 2 =(XX0,1X) v 11 merged =0X0v 12 merged =1Xv 21 merged = 1XX 1

[0118] v 3 =(0XX,X0)v 11 merged =0X0v 12 merged = 10V 31 merged =0X1 2

[0119] v 4 =(1XX,XX) v 21 merged = 1XX v 12 merged =10

[0120] v 5 =(0XX,X0)v 31 merged = 0XX v 12 merged =10

[0121] v 6 = (XX1, 1X) v 31 merged = 0X v 12 merged =10

[0122] (a) (b) (c) (d) (e)

[0123] The basic idea presented above is to use merge padding as an ATPG padding strategy. Mathematically, it can be proved that the use of combined filling obtains the best result, that is, the longest possible sequence of consistent vectors is obtained, thereby obtaining the longest repetition count value. The analysis and simulation results are as follows:

[0124] For repeat-per-pin (ie, a port contains a single pin), the merge fill is the same...

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Abstract

A method and apparatus for compressing test vector data for use in testing a logic product, wherein original test vector data is generated in the form of two or more sequences of bits including "care" bits and "don't care" bits. The test vector data is then compressed by comparing corresponding bits of two or more subsequent vectors and merging the two or more vectors into a single vector representative thereof if all of the corresponding bits of the two or more vectors are found to be compatible. Compatibility of two bits is achieved if they do not have specifically incompatible or opposite values. <IMAGE> <IMAGE>

Description

technical field [0001] The present invention relates to a method and apparatus for data compression, more particularly but not necessarily exclusively, to a method and apparatus for reducing the The amount of test data used for such logic products or compress the test data to save the amount of computer memory, disk storage and save the time required to test such products. Background technique [0002] Every integrated circuit (IC) manufactured must be thoroughly tested for manufacturing defects before it is shipped to the subscriber. Conventional methods for testing ICs include automatically generating test patterns using ATPG (Automatic Test Pattern Generation) tools, and applying these test patterns to ICs and Design for Test (DfT) structures within chips using ATE (Automatic Test Equipment). [0003] A common DfT technique for digital logic circuits is 'scan design', which allows the flip-flops in the circuit to be configured as serial shift registers ('scan chains') du...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/319
CPCG01R31/31921
Inventor H·P·E·弗兰肯H·D·L·霍尔曼
Owner NXP BV