Memory element and method of manufacturing thereof
A storage element and storage device technology, which can be used in semiconductor devices, semiconductor/solid-state device manufacturing, information storage, etc., and can solve problems such as increased power consumption
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Embodiment approach 1
[0045] An example of the structure of the memory element of the present invention will be described with reference to FIGS. 1A to 1C. The memory element shown in FIG. 1A includes a first conductive layer 110 , a metal oxide layer 111 , a semiconductor layer 112 , an organic compound layer 113 , and a second conductive layer 114 . The metal oxide layer 111, the semiconductor layer 112, and the organic compound layer 113 are sandwiched by the first conductive layer 110 and the second conductive layer 114, and the metal oxide layer 111 is in contact with the first conductive layer 110, and the semiconductor layer 112 is in contact with the second conductive layer 114. The metal oxide layer 111 is provided in contact.
[0046] As the first conductive layer 110 and the second conductive layer 114, highly conductive metals, alloys, compounds, etc., which are composed of a single layer or a laminated structure can be used.
[0047]For example, indium tin oxide (hereinafter referred ...
Embodiment approach 2
[0081] In this embodiment mode, a semiconductor device including the memory element of the present invention, typically a memory device, will be described with reference to the drawings. Here, a case where the structure of the memory device is a passive matrix type is shown.
[0082] FIG. 4A shows an example of the structure of the semiconductor device shown in this embodiment mode. The semiconductor device 400 includes a memory cell array 411 in which memory elements 401 are arranged in a matrix, decoders 412 and 413 , a selector 414 , and a read / write circuit 415 . Note that the structure of the semiconductor device 400 shown here is just an example, and other circuits such as sense amplifiers, output circuits, buffers, and the like may also be included.
[0083] Note that the decoders 412 and 413, the selector 414, the read / write circuit 415, the interface, and the like may be formed on the substrate similarly to the memory element, or may be provided externally as an IC c...
Embodiment approach 3
[0107] In this embodiment mode, a semiconductor device including the memory element of the present invention will be described with reference to FIGS. 7A to 7C . Note that, specifically, an active matrix type memory device will be described.
[0108] FIG. 7A shows an example of the structure of the semiconductor device shown in this embodiment mode. The semiconductor device 700 includes a memory cell array 711 , decoders 712 and 713 , a selector 714 , and a read / write circuit 715 . In this memory cell array 711, memory cells 701 are arranged in a matrix. Note that the structure of the semiconductor device 700 shown here is just an example, and other circuits such as sense amplifiers, output circuits, and buffers may be included.
[0109] Note that the decoders 712 and 713, the selector 714, the read / write circuit 715, the interface, and the like may be formed on the substrate similarly to the memory element, or may be provided externally as an IC chip.
[0110] The storage ...
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