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An emulator that implements flash page erase emulation

An emulator and emulation chip technology, applied in the field of emulators, can solve problems such as slow single-step running speed and affect debugging work efficiency, and achieve high debugging efficiency and be beneficial to debugging efficiency.

Inactive Publication Date: 2011-11-30
SHANGHAI HUAHONG INTEGRATED CIRCUIT
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AI Technical Summary

Problems solved by technology

However, this waiting time must be increased enough for the completion of the FLASH page erase, which is several to dozens of times longer than the original instruction execution time, which will cause the user program to be executed in the single-step operation mode. The running speed of each step is very slow, which will greatly affect the efficiency of debugging work

Method used

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  • An emulator that implements flash page erase emulation
  • An emulator that implements flash page erase emulation

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Embodiment Construction

[0012] As shown in the drawings, the emulator 1 implemented by the method of the present invention includes an emulation chip 2 and a management module 3 . There is a FLASH module 4 consistent with the product chip in the emulation chip 2 . The management module 3 is connected to the emulation chip 2 through a control signal 5, and through the control signal 5, the management module 3 can control whether the emulation chip 2 is in the running mode or the monitoring mode. The emulation chip 2 also has a waiting signal 6 connected to the management module 3. When the emulation chip 2 is in the running mode, if the emulation chip 2 sends the waiting signal 6 to the management module 3, the management module 3 will not pass the waiting signal 6 during the effective period. The control signal 5 controls the switching of the operating mode of the emulation chip 2 to keep it in the running mode; when the waiting signal 6 is invalid, the management module 3 controls the switching of t...

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Abstract

The invention discloses an emulator for realizing FLASH page erasing, comprising an emulation chip and a management module. The management module is connected with the emulation chip through a control signal, and the emulation chip is controlled to be in the running mode or the monitoring mode through the control signal management module. The emulation chip also has a waiting signal connected to the management module. When the emulation chip is in the running mode, if the emulation chip sends a waiting signal to the management module, the management module keeps the emulation chip in the running mode while the waiting signal is valid. When the emulation chip executes the user program statement in the running mode, it will judge whether it is the statement that triggers the FLASH page erase operation, if not, it will not send a wait signal to the management module; The emulator of the present invention can not only ensure the functional correctness of single-step operation of the FLASH page erasing program segment, but also can debug other user program instructions in a single-step operation mode efficiently and quickly.

Description

technical field [0001] The invention relates to an emulator, in particular to an emulator capable of realizing the FLASH page erasing emulation function. Background technique [0002] When developing and debugging user programs in processor chips, the tools used by program developers are emulators with emulated chips. At present, many processor chips have FLASH memory, which is the same as the characteristics of a single FLASH chip. Most of the FLASH in the chip still has the function of erasing pages in units of pages. One page can be 32, 64, or 128 words. Sections and other sizes, depending on the specific design requirements of FLASH. The so-called page erasure of FLASH is triggered by a set of program statements to perform an automatic clearing operation on all data in a page specified inside the FLASH. The erasing process takes a certain amount of time, depending on the size of the page, from a few milliseconds to several It ranges from ten milliseconds, which is much...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/36
Inventor 许国泰
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT
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