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Minimum value computing device for LDPC decoder and constructing method thereof

A calculation device and minimum value technology, applied in the field of channel coding, can solve the problem that the sorting-query minimum value calculation method cannot be well applied to LDPC decoders, limit the working speed and data throughput of decoders, and have no hardware Realize problems such as structure and construction method, achieve the effect of improving work rate and data throughput, reducing computational complexity and logic resource occupation, and simplifying design complexity

Active Publication Date: 2009-07-08
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, when calculating the minimum value of these λ sets separately, the computational complexity is λ 2 magnitude
When λ is large, the minimum value calculation in the LDPC decoder dramatically increases the complexity of LDPC decoding, and constitutes a critical delay path of the decoder, limiting the working speed and data throughput of the entire decoder
[0056] If the minimum value calculation in the HPU is completed by sorting and querying, there is no suitable hardware implementation structure and construction method, which will increase the computational complexity
Therefore, the sort-query minimum calculation method is not well applied to the LDPC decoder

Method used

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  • Minimum value computing device for LDPC decoder and constructing method thereof
  • Minimum value computing device for LDPC decoder and constructing method thereof
  • Minimum value computing device for LDPC decoder and constructing method thereof

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Embodiment 1

[0124] The minimum calculation device of the LDPC decoder HPU in this embodiment is an irregular hierarchical minimum calculation device, and the comparison and selection unit D of the first-level sorting unit 1 A 1 Select the number λ of variable node information input for the HPU. The mapping from the output of the first-level sorting unit to the input of the subsequent sorting unit is determined according to the number λ of variable node information input by the actual HPU, so that ρ j (0≤j≤λ-1) divided A 1 The number of variable node information in each set in a set is as small as possible (preferably 2 or 3). For simple explanation, this embodiment takes the number λ of the variable node information input by the HPU as 6 as an example, and the first-level sorting unit adopts 6 comparison and selection units D 1 , and output six sets of minimum values, second minimum values ​​and minimum value serial numbers {min, submin, index}, and the sorting unit 201 and query unit ...

Embodiment 2

[0140] The minimum value calculation device of the LDPC decoder HPU in this embodiment is a regular hierarchical minimum value calculation device. The method of constructing the minimum value calculation device of the LDPC decoder HPU through rule classification and the structure of the minimum value calculation device of the LDPC decoder HPU are given below.

[0141] The construction method of the minimum calculation device of the LDPC decoder HPU in the present embodiment comprises the following steps:

[0142] 1) Determine the radix S of the multi-level sorting unit classification, S is an integer greater than 1 and less than the number λ of variable node information input by the HPU, in order to ensure lower computational complexity, usually take S as 2 or 3;

[0143] 2) Obtain the number of stages of the multi-level sorting unit (in Represents the smallest integer not less than x), and starts to build sorting units at all levels;

[0144] 3) select comparison and s...

Embodiment 3

[0152] The minimum value calculation of the hierarchical LDPC decoder HPU of the present invention can (but not limited to) be designed according to the pipeline mode, and only need to register the corresponding signals with registers at the output end of the corresponding every-level sorting unit during the pipeline design, and it can be significantly Improve the clock frequency and data throughput rate of HPU and LDPC decoder.

[0153] The minimum value calculation device structure of the LDPC decoder HPU is described below with the number λ of the variable node information input by the HPU being 27. like Figure 4 As shown, the device is divided into a multi-level sorting unit 401 and a query unit 402 .

[0154] The multi-level sorting unit 401 is further divided into Levels (411, 412, 413). Level 1 sorting unit 411 contains (i.e. 9) comparison selection units D 1 , divide the 27 input variable node information into 9 sets, respectively {ρ 0 , ρ 1 , ρ 2}, {ρ 3 , ...

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Abstract

The invention relates to a minimum value calculator of an LDPC encoder and a construction method thereof. The minimum value calculator comprises a multilevel ordering unit and an inquiry unit. The multilevel ordering unit complements the ordering step in an ordering-inquiry type minimum value calculating method in a hierarchical manner; the hierarchical manner divides an input set in a recursive manner; a plurality of sets obtained in each division are processed by calculating operation on a minimum value, a secondary minimum value and minimum value serial number so as to form one level, thereby forming a hierarchical type hardware configuration which is a regular hierarchical configuration or an irregular hierarchical configuration; and the construction method of the minimum value calculator based on the regular hierarchical configuration forms the multilevel ordering unit in a stepwise manner by determining a hierarchical cardinal number. The minimum value calculator and the construction method thereof simplify the HPU design of the LDPC encoder, reduces the HPU hardware source consumption, and is easy to perform pipelining design on HPU of the LDPC encoder, thereby partitioning a key path of HPU, and increasing the working speed and the data throughput of the LDPC encoder.

Description

technical field [0001] The invention relates to the field of channel coding, in particular to an LDPC decoder minimum value calculation device and a construction method thereof. Background technique [0002] The low density parity check (LDPC) channel coding scheme was first proposed by Gallager in 1962 (Robert G. Gallager, "Low-density parity-check codes," IRE Transaction on Information Theory, IT-18, pp .21-28, Jan. 1962). Because the calculation of its encoding and decoding is very complicated relative to the processing capabilities of electronic devices at that time, it did not attract people's attention again until the 1990s. And because of its outstanding coding performance, it is more and more widely used in communication and broadcasting systems and standards. As a linear block code, the LDPC code is described by its check matrix H, and all its codewords are orthogonal to the row space of the check matrix H. The check matrix density of the LDPC code is low, that i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
Inventor 彭克武江南杨知行潘长勇
Owner TSINGHUA UNIV
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