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JPEG-LS run length coding hardware implementation method

A technology of 1. JPEG-LS and run-length coding, which is applied in the field of JPEG-LS run-length coding based on FPGA, can solve problems not involving run-length coding FPGA hardware implementation, etc., and achieve good real-time performance

Inactive Publication Date: 2010-07-21
BEIJING RES INST OF SPATIAL MECHANICAL & ELECTRICAL TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the patent does not involve the FPGA hardware implementation of run-length encoding

Method used

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  • JPEG-LS run length coding hardware implementation method
  • JPEG-LS run length coding hardware implementation method
  • JPEG-LS run length coding hardware implementation method

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Embodiment

[0168] Take two times of encoding RUNcnt=5, and EOLine is 0 as an example.

[0169] (1) Using standard algorithm

[0170] ●The first encoding RUNcnt=5, EOLine=0

[0171] ■ a step

[0172] At this time RUNindex=0, that is 2 J[RUNIndex] = 2 J[0] = 2 0 = 1

[0173] According to the encoding process, RUNcnt≥2 J[RUNIndex] That is, 5≥1, output bit '1'; at the same time RUNcnt=RUNcnt-2 J[RUNIndex] =4; RUNindex becomes 1 after adding 1.

[0174] Since RUNcnt≥2 J[RUNIndex] That is, 4≥1, continue to execute step a, output bit '1'; at the same time RUNcnt=RUNcnt-2 J[RUNIndex] = 3; RUNindex increases by 1 to become 2.

[0175] Since RUNcnt≥2 J[RUNIndex] That is, 3≥1, continue to execute step a, output bit '1'; at the same time RUNcnt=RUNcnt-2 J[RUNIndex] = 2; RUNindex plus 1 becomes 3.

[0176] Since RUNcnt≥2 J[RUNIndex] That is, 2≥1, continue to execute step a, output bit '1'; at the same time RUNcnt=RUNcnt-2 J[RUNIndex] =1; RUNindex is increased by 1 to become 4.

[0177...

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Abstract

The invention discloses a JPEG-LS run length coding hardware implementation method which improves and optimizes the standard procedure of JPEG-LS run length coding, introduces coding mapping operation, implements coding by comparing a table look-up operation pipeline, and solves cycle coding in multiple clock cycles in an original algorithm; in addition, since only residual coding adopts index value RUN index single-cycle update operation and tour length coding and residual coding adopt index value RUNindex two-cycle update operation, coding speed is improved. The method is completely implemented by FPGA, has the advantages of full pipeline and good real time property, and can be applied to hardware algorithm of JPEG-LS lossless and near lossless compression.

Description

technical field [0001] The invention belongs to the field of image processing, and relates to a method for realizing JPEG-LS run-length coding based on FPGA. Background technique [0002] JPEG-LS (Information Technology-Lossless / near-lossless compression standard for continuous-tone still images) algorithm is an image compression standard formulated by the Joint Photographic Experts Group. Compared with other compression algorithms, JPEG- LS has higher compression performance in the field of lossless and near-lossless compression, and has a wide range of applications in medical treatment, remote sensing image communication and other fields that require high image quality recovery. The JPEG-LS standard algorithm uses two modes to encode pixels - the run-length mode and the normal mode. The normal mode performs Golomb encoding on the prediction residual, while the run-length mode encodes the run-length, which is used to compress the flat area of ​​the image, thus smoothing Im...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N7/26H04N1/41H04N19/192H04N19/42
Inventor 陈大羽王琨雷宁武文波张媛
Owner BEIJING RES INST OF SPATIAL MECHANICAL & ELECTRICAL TECH
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