16 results about "Hardware algorithm" patented technology

The invention discloses a power management system adapted to an extremely low temperature environment. Through a multi-level self-adaptive heating mechanism and a hardware-algorithm cooperative control strategy, stable operation in an extremely low temperature environment is realized. The power manager integrates a closed-loop temperature control system and double-order starting logic of'hardware priority-software takeover ', the special charger adopts a distributed temperature sensing and space temperature field reconstruction technology, reliable charging and discharging management under the extreme environment of-68 DEG C is achieved through cooperation of the closed-loop temperature control system and the space temperature field reconstruction technology, heating extra power consumption is reduced by 90% or above, and the maximum temperature difference of a battery bin is smaller than or equal to 2 DEG C; and the cold start success rate is 100%. The power supply system can be widely applied to extremely-low-temperature individual power supply systems, extremely-low-temperature battery packs and other scenes, and the core technical bottleneck of the power supply system in an extreme environment is solved.

Technologies for compilers that implement non-power of two Fast Fourier Transform (FFT) algorithms are described. The non-power of two FFT algorithm uses a recursive function to generate a hardware design of a set of compute blocks of a fixed-point digital signal processor (DSP) and routing data between the compute blocks. The compiler receives input specifying a sequence of indexes and a bit width of the fixed-point DSP and performs a process. The process splits the sequence using a recursive loop, determines a number of multiplications in the hardware design, and generates a trace graph of the non-power of two FFT algorithm. The process is entered via the recursive function and exists when the recursive loop decrements to a specified value corresponding to a Radix-3 or Radix-2. The compiler outputs data, including the hardware design, the number of multiplications in the hardware design, and the trace graph.

The invention relates to the technical field of new energy automobile battery teaching, and discloses a full-link virtual-real linkage battery simulation teaching system, which comprises hardware simulation, 3D / VR simulation software and an algorithm verification and fault simulation module, and is characterized in that the hardware simulation module comprises a modular insulation rack, a high-precision battery simulator, a waterway heat dissipation system and VR interaction equipment; equipment interconnection is realized through the communication module; the 3D / VR module supports 3D dynamic display and immersive operation simulation of the battery pack; the fault simulation module can issue a fault signal and is linked with hardware; the algorithm verification module supports fault data injection and user-defined algorithm operation; the system collects hardware data through the BMS controller and transmits the hardware data to the software system through the communication module, virtual and real data synchronization and a whole-process teaching closed loop are achieved, practical training safety, practical operation authenticity and teaching depth are considered, and the system is suitable for multi-scene battery teaching.

The invention discloses a dynamic range compression image enhancement algorithm for an ultrahigh-resolution high-dynamic image and hardware thereof, and the algorithm comprises the steps of RGB-XYZ color space conversion, n-frame average maximum brightness statistics, adaptive brightness zooming, dynamic mapping factor calculation, segmented low-bit mapping and the like, and achieves high-dynamic range precise compression. Hardware adopts a modular design, and ASIC / FPGA deployment is supported. According to the method, the dynamic range compression from the high-bit high-dynamic image to 8-bit display is efficiently completed, the details of a dark part and a medium-brightness region are reserved to the maximum extent, and the visual effect of an original scene is restored; a traditional high-complexity algorithm is abandoned, the calculation amount and the on-chip storage cost are reduced by simplifying the design, and low-time-delay and low-power-consumption deployment is achieved; and adaptive parameters and dynamic mapping are adopted, so that the problems of overexposure and underexposure caused by a fixed mapping curve are avoided, the quality of a reconstructed image is remarkably improved, and the high-quality display requirement in a low-delay and low-power-consumption scene is perfectly met.

The invention relates to the technical field of numerical calculation and hardware algorithm implementation, in particular to a segmentation strategy-based high-precision logarithmic function implementation method, which comprises the following steps of: carrying out standardization processing on an input floating-point number, generating a threshold signal for path selection based on a relationship between an index and a mantissa of the floating-point number, and then, carrying out segmentation on the threshold signal; performing sub-interval division on the standardized data, determining corresponding sub-interval numbers, selecting a sub-interval starting point as a polynomial approximation reference point, generating parameter data for polynomial calculation and third-order Taylor expansion calculation, performing numerical format unification and shift alignment processing on the parameter data, and then obtaining a polynomial approximation reference point; the method comprises the following steps: respectively performing polynomial calculation and Taylor expansion calculation to obtain a polynomial fixed-point result and a Taylor expansion temporary result, performing normalization and rounding processing on calculation results to ensure that output meets floating point format requirements, and finally realizing path selection according to a threshold signal and outputting a final logarithmic function result. Therefore, the calculation precision and the operation efficiency are effectively considered.

The invention relates to the technical field of integrated circuit design, and particularly discloses a device and method for accelerating high-precision ADC data operation, and the device comprises a bus which comprises an address bus and a data bus; the hardware algorithm accelerator comprises an address mapping logic module, an input and output mapping module, a register module and an algorithm acceleration core function module; the address mapping logic module is used for splitting an address access request from an address bus into a read-write access command of the register module and a parameter and operation command of the algorithm acceleration core function module; the register module includes a configuration register, a plurality of operand registers, and a configuration register. According to the method and the device, the address access request from the address bus is divided into two parts, meanwhile, calculation input and output are selected through address mapping, a calculation result can be directly imported into a newly-initiated calculation input end, read-write of a processor to an operand register can be reduced, and the calculation efficiency is improved.

The invention provides a laser wavelength stabilizing device and method based on a special TEC controller. The device comprises a core chip module, a temperature setting module, a temperature feedback module, a TEC load module, a power supply and protection module and a PID compensation module, wherein the core chip module adopts an ADN8834 or ADN8835 chip to construct a hardware PID closed-loop control architecture; the method comprises the steps that a target temperature voltage signal is output through the temperature setting module, the temperature feedback module collects the temperature of the laser in real time and converts the temperature into feedback voltage, the core chip module compares the target signal with the feedback signal based on a hardware PID algorithm, a regulation and control current is output to drive the TEC load module to achieve refrigeration / heating, and control performance is optimized in cooperation with the PID compensation module. The invention is applied to the technical field of laser temperature control and wavelength calibration.

This invention discloses a target tracking test method for wireless detection devices based on multi-dimensional dynamic scenarios, belonging to the interdisciplinary field of target detection and artificial intelligence. The method includes: Step 1, generating a high-fidelity target tracking dynamic scenario through hierarchical modeling; Step 2, generating structured test data based on a parameterized space; Step 3, performing multi-dimensional performance evaluation on a verification platform: inputting the generated I / Q data into the algorithm under test deployed on the platform, and calculating five types of indicators in real time; Step 4, dynamically optimizing the test scenario based on the evaluation results. This invention addresses the shortcomings of existing technologies in dynamic scenario reproduction, algorithm evaluation dimensions, and hardware-in-the-loop verification by constructing a configurable electromagnetic environment model, a multi-dimensional evaluation indicator system, and a hardware-in-the-loop verification architecture, thereby quantitatively evaluating the real-world capabilities of algorithms in complex dynamic environments.

The application relates to the technical field of integrated circuit design, and particularly discloses an apparatus and method for accelerating high-precision ADC data operation, which comprises a bus including an address bus and a data bus; a hardware algorithm accelerator including an address mapping logic module, an input-output mapping module, a register module and an algorithm acceleration core function module; the address mapping logic module is used for splitting an address access request from the address bus into two parts of a read-write access command of the register module and parameters and operation commands of the algorithm acceleration core function module; and the register module comprises a configuration register, a plurality of operand registers and the configuration register. According to the application, the address access request from the address bus is split into two parts, the calculation input and output are selected through address mapping, the calculation result can be directly introduced into a newly initiated calculation input end, the read-write of the operand register by the processor can be reduced, and the operation efficiency is improved.

The invention discloses an intelligent detection, identification and tracking system and method based on a domestic micro-processing platform, and belongs to the technical field of embedded artificial intelligence and computer vision. The system adopts a chip of National Coriolis Microelectronics 7608 as a core, and combines a lightweight detection model, a high-precision identification network and a fusion tracking algorithm; through dynamic memory allocation, mixed precision reasoning and a self-adaptive tracking mechanism, the 25FPS processing capability under the resolution of 1080p is realized, the end-to-end delay is lower than 50ms, and the power consumption is lower than 3W. According to the system, low-power-consumption and high-precision end-side intelligent processing is realized through hardware-algorithm collaborative optimization, and the system is suitable for scenes of security monitoring, intelligent transportation, industrial automation and the like.

The invention discloses an FPGA-based underwater target recognition convolutional neural network acceleration method, and aims to solve the problem that a convolutional neural network in underwater edge equipment is dense in calculation and limited in storage. A lightweight network formed by three layers of depth separable convolution and two layers of full connection layers is designed, parameter lightweight is realized through a batch normalization parameter fusion formula and is converted into a semi-precision floating point format, and an acceleration circuit for deep convolution block calculation and full connection layer merging IP core packaging is designed based on an FPGA. And parallel strategies such as loop expansion and pipeline optimization are combined to improve the calculation efficiency. The innovation points to be protected are a collaborative application method of deep separable convolution and parameter lightweight processing, a circuit design strategy of realizing convolution layer block calculation and full connection layer combination by the FPGA, and a parallel optimization strategy combination of loop expansion and array segmentation. And low-power-consumption real-time reasoning of underwater target recognition is realized through collaborative design of a hardware algorithm.

The invention relates to the technical field of motor control, in particular to a three-phase six-wire motor controller, which comprises an independently researched and developed motor driving chip P2850, a power supply module, a sensor group, a communication interface, a driving circuit, a power module and a heat dissipation system. The P2850 chip integrates a special hardware accelerator and an MCU core, executes a hardware FOC algorithm, and accurately regulates and controls six-path phase current in real time; according to the power module, 12 power semiconductor switching devices form two independent three-phase full-bridge inverter circuits. By the adoption of the technical scheme, high-order harmonic current can be effectively restrained, the operation efficiency of the motor is improved, vibration noise is reduced, the torque output and speed regulation range is widened, and the system reliability and the fault-tolerant capability are enhanced.

The invention provides a side channel attack resistant post-quantum cryptographic algorithm security implementation method and system, and belongs to the technical field of cryptographic hardware security. In password hardware, a hardware-algorithm collaborative abstraction layer is used as a core control hub, and the method comprises the following steps of: constructing a logically isolated security execution environment supported by protected hardware; loading a security algorithm image subjected to side channel reconstruction resistance; in the process of executing the algorithm mapping, the abstraction layer dynamically schedules hardware resources and synchronously injects randomized disturbance; meanwhile, physical side channel signals are collected in real time through a safety monitoring unit; and when the signal is judged to be abnormal, feeding back to the abstraction layer to dynamically adjust a disturbance strategy or switch a standby execution path. Through cooperation and dynamic adjustment of software and hardware resources, the problems of protection design lagging, resource static splitting and lack of adaptive ability in the prior art are solved, efficient active security defense is achieved, and the protection ability of post quantum cryptography hardware for resisting side channel attacks is improved.

The application discloses a kind of supporting password card algorithm library operation implementation method and related device, algorithm library has software algorithm interface and hardware algorithm interface, algorithm library calls software algorithm interface and / or hardware algorithm interface to complete preset operation task, wherein: software algorithm interface is connected with server signal, to realize preset operation task in server by preset algorithm;Hardware algorithm interface is connected with password card signal, to realize preset operation task in password card by preset algorithm;Software algorithm interface and hardware algorithm interface are compatible with each other.Compared with prior art, by setting software algorithm interface and hardware algorithm interface in algorithm library simultaneously in the application, user can select suitable use mode according to actual demand, and software algorithm interface and hardware algorithm interface are compatible with each other, software algorithm interface and hardware algorithm interface can cooperate to share load, deployment cost is low, and it is more flexible and convenient to deploy.

The application discloses a multi-interface compatible SM3 / SM4 algorithm hardware module instruction translation method and related devices, including a host end, a translation chip end and a hardware algorithm end, wherein the host end and the translation chip end interact information, and the translation chip end and the hardware algorithm end interact information, the method and related devices have the characteristics of strong hardware form compatibility, high interface protocol adaptability and low calling complexity.

The application discloses a kind of encoding method, positioning method, device and magnetic tape, belongs to storage technical field.The method is applied to magnetic tape, magnetic tape includes first servo tape, second servo tape and first data tape, first servo tape, first data tape and second servo tape are sequentially stacked arrangement, encode first information on first servo tape;Encode second information on second servo tape, second information is used to identify first data tape with first information, utilize the characteristics that servo read head simultaneously reads two servo tapes, by the mode of encoding, the information used to identify data tape is divided into two partial information and encoded on two adjacent servo tapes, facilitate subsequent in the process of positioning to magnetic tape, the information of two servo tapes can be identified data tape in combination, without calculating offset, can accurately position data tape, simplify the complexity of decoding hardware algorithm, reduce external factors to cause system instability, improve positioning accuracy.