63 results about "Hardware algorithm" patented technology

A system and method intelligently control power consumption of distributed services using a computer system that provides independent computing elements each capable of entering a power saving mode. In accordance with the present invention, three different algorithms are disclosed. The first algorithm is a reduced load power saving algorithm. As the load decreases, duplicate instances of services can be gracefully suspended and the host processor cards hosting these instances can enter a power saving mode. The second algorithm is a priority-based power consumption reduction algorithm. If power consumption must be reduced, services having less of a contribution to revenue are suspended before components that having a higher contribution to revenue. The third algorithm is a minimal power-consuming redundant computing hardware algorithm that allows a “cold spare” host processing card to be pressed into service if another card fails.

A system and method to intelligently control power consumption of distributed services using a computer system that provides independent computing elements each capable of entering a power saving mode. The first algorithm is a reduced load power saving algorithm. As the load decreases, duplicate instances of services can be gracefully suspended and the host processor cards hosting these instances can enter a power saving mode. The second algorithm is a priority-based power consumption reduction algorithm. If power consumption must be reduced, services having less of a contribution to revenue are suspended before components that having a higher contribution to revenue. The third algorithm is a minimal power-consuming redundant computing hardware algorithm that allows a “cold spare” host processor card to be pressed into service if another card fails.

The invention relates to a high-frequency electrotome generator based on an FPGA (Field Programmable Gata Array). A power supply provides direct-current voltage signals to a radio frequency generation module; the direct-current voltage signals are subjected to resonant amplification of the radio frequency generation module and rectification of a half bridge circuit to be changed to high-voltage alternating-current radio frequency singles to be output, and then the output signals are transmitted to a biological organization by a radiation electrode and a backward channel; an impedance detection unit is used for detecting the impedance of the biological organization and transmitting impedance parameters to an FPGA main control unit; according to the impedance parameters, the FPGA main control unit regulates the duty ratio of SPWM (Sinusoidal Pulse Width Modulation) waves in real time; and then the SPWM waves are output to the radio frequency generation module. A controller disclosed by the invention can realize accurate control and is high in response speed, easy to modify, capable of programming in situ, strong in universality and stable in performance; and more importantly, by virtue of the large-scale FPGA, a microprocessor, a special hardware algorithm unit, a special waveform generation unit and a signal acquisition and processing unit are all integrated on a single chip, so that the high-frequency electrotome generator becomes a special integral electronic control system.

The present invention discloses a bus monitor for enhancing SOC system security and a realization method thereof. The bus monitor disposed between a system bus and a system control unit includes a configuration unit, a condition judgment unit, an effective data selection unit, a hardware algorithm unit and a comparative output unit. Without affecting the bus access efficiency, the present invention provides the method capable of immediately monitoring the bus behavior, and the detection system notices whether a particular bus access serial behavior is changed due to an accidental fault or intentional attacking fault. If the particular bus access serial behavior is changed, the present invention warns the system to adopt a suitable security measure to prevent the security hidden trouble and leakage of classified information due to the incorrect system security process.

A system and method intelligently control power consumption of distributed services using a computer system that provides independent computing elements each capable of entering a power saving mode. In accordance with the present invention, three different algorithms are disclosed. The first algorithm is a reduced load power saving algorithm. As the load decreases, duplicate instances of services can be gracefully suspended and the host processor cards hosting these instances can enter a power saving mode. The second algorithm is a priority-based power consumption reduction algorithm. If power consumption must be reduced, services having less of a contribution to revenue are suspended before components that having a higher contribution to revenue. The third algorithm is a minimal power-consuming redundant computing hardware algorithm that allows a “cold spare” host processing card to be pressed into service if another card fails.

The invention provides a dependable computing based process control method. The process control method includes that a system is powered and a BIOS (basic input/output system) is started; the BIOS drives an operating system bootstrap program to start; the bootstrap program drives an integrity measurement module in an inner nuclear layer to start; the integrity measurement module drives a process control module in an operating system layer to start; the process control module is used for judging ordinary files, critical files and dynamic resources in process; the process control module and the integrity measurement module are used for controlling the ordinary files, the critical files and the dynamic resources to realize protection of the program. By the method, the files related to process operation are subjected to protection based on the dependable computing platform hardware algorithm, static files and the dynamic files are protected, permission of accessed files and mapping relation label pages are defended, and protective means are stereo and include the aspects of direct encryption storage, and inputting credibility quantity into a dependable computing platform register and the like, so that the process can be effectively controlled.

The invention discloses a JPEG-LS run length coding hardware implementation method which improves and optimizes the standard procedure of JPEG-LS run length coding, introduces coding mapping operation, implements coding by comparing a table look-up operation pipeline, and solves cycle coding in multiple clock cycles in an original algorithm; in addition, since only residual coding adopts index value RUN index single-cycle update operation and tour length coding and residual coding adopt index value RUNindex two-cycle update operation, coding speed is improved. The method is completely implemented by FPGA, has the advantages of full pipeline and good real time property, and can be applied to hardware algorithm of JPEG-LS lossless and near lossless compression.

The invention discloses an infrared image based hardware processing algorithm effectiveness performance evaluation device and method. The infrared image based hardware processing algorithm effectiveness performance evaluation device is formed by an original infrared image input end, a gigabit network transmission module, an infrared image hardware algorithm processing performance evaluation board, an infrared image output end and an evaluation result display. The infrared image based hardware processing algorithm effectiveness performance evaluation method comprises transmitting an original infrared image into an upper computer and the infrared image hardware algorithm processing performance evaluation board; determining the performance evaluation index information of the infrared image after processing through the infrared image hardware algorithm processing performance evaluation board; displaying an evaluation result through the evaluation result display. According to the infrared image based hardware processing algorithm effectiveness performance evaluation device and method, the effect of the infrared image after the processing of different hardware algorithms can be objectively evaluated, the comparison can be performed on the infrared image after the processing by the algorithm in the upper computer and the hardware algorithm in the infrared image hardware algorithm processing performance evaluation board, and designers can further optimize and improve the hardware algorithms of the infrared image processing algorithm according to the comparison of the two processing results.

The invention provides an algorithm verification platform and method. The platform comprises a computer, an algorithm verification module, and a sequential control module; the computer outputs testingvideo image data and frame-extracting interval parameter, refreshing frequency of a display panel and an output selection parameter to the algorithm verification module; the algorithm verification module performs frame extraction on the testing video image data according to the frame-extraction interval parameter to obtain the second video image data, and processes the second video image data according to a preset video image hardware algorithm to obtain the third video image data, and encodes the second or the third video image according to the selection output parameter and then outputtingthe encoded second or third video image data to the sequential control module; the sequential control module controls the display panel to display the corresponding video image. The verification platform provided by the invention can verify the actual improvement effect on the display panel by the video image hardware algorithm without performing the frequency lowering output on the second or third video image data.

Multiple cipher hardware algorithms are run in parallel over an input stream. For example, one algorithm can process the input stream using an old cipher key while a parallel algorithm processes the input stream using the current cipher key. Alternatively, multiple cipher operations can be performed in parallel enabling a receiver to determine which cipher algorithm was employed in encrypting a data packet.

A method of generating complex exponentiation and logarithms in hardware is described that uses half the number of bits of lookup tables as the state-of-the-art. By splitting up each of the iterations into more simplified stages or using more iterations, the amount of precomputed information that must be held by the circuitry is reduced. This allows synthesis tools to take this more succinct logical description of the algorithm and make it into efficient gate level logic for fabrication into more compact integrated circuitry.

The invention relates to a full impedance distance protection method based on an FPGA. The method includes the steps of 1 calculating impedance protection, 2 adopting an upper computer for definite value matching, 3 adopting a shifting multiplication and division method, 4 adopting a state machine for time division multiplexing, 5 testing the impedance protection characteristic and 6 carrying out simulation testing. Based on a hardware platform of the FPGA, the FPGA is used for calculating the processing speed of improving the hardware protection logic in parallel at high speed to ensure the safety and reliability of motions. By the adoption of a full impedance distance protection hardware algorithm based on the FPGA, judgment processes of starting elements such as positive sequence voltage, negative sequence voltage and currents are reduced, and real-time calculation and logical judgment are carried out to further protect the reliability of relay protection motions.

The invention relates to a smart card system which comprises a central processing unit (CPU), a hardware algorithm module used for algorithm calculation, a memorizer used for storing program and data, a random access memory (RAM) and a firewall module, wherein the RAM module is used for providing algorithm running space as ordinary RAM used for a central processor unit (CPU) for a smart card hardware algorithm module. The firewall module is used for providing safeguard for a smart card algorithm RAM module. Due to the smart card system, in the process of algorithm running, only the hardware algorithm module accounts for the RAM. On the one hand, efficiency of the algorithm running is greatly improved, on the other hand, only the hardware algorithm module can read middle results of the algorithm running, and therefore the hacktivism that an illegal program uses CPU to maliciously read the results of the algorithm running to speculate a secret key or algorithm implementation is eliminated, and absolutely reliability of the hardware algorithm module is ensured.

The present invention relates to the field of data processing, and discloses a high-speed parallel processing architecture for a data center. The high-speed parallel processing architecture comprises a plurality of processing boards, and is characterized in that each processing board comprises at least two transceivers, at least one FPGA programmable logic chip and at least two processors (CPUs), wherein the CPUs are connected with with the FPGA chip through CPU high-speed serial interfaces; and a plurality of high-speed serial transceiver cores and a plurality of corresponding coprocessors (MCUs) are arranged in the FPGA chip; a plurality of embedded memories corresponding to each coprocessor MCU are embedded into the FPGA ; and each embedded memory is configured to be in a dual-port mode capable of reading and writing. According to the high-speed parallel processing architecture, an embedded CPU+FPGA architecture is realized; high-speed parallel hardware algorithms are realized, so that processing ability of basic computing elements is greatly improved, and system schedule delay is reduced.

The invention discloses a self-calibration method for a ray collimator and a system thereof. The method comprises the steps of calculating an offset of a current X-ray collimator according to a previous scanning condition and detector data of previous exposure; according to the current scanning condition and the offset of the current X-ray collimator, adjusting the offset of the X-ray collimator,so that X-rays cover an entire detector. Since all calibration methods can be implemented by software of a reconstruction machine, there is no need to increase the hardware cost to ensure communication between the detector and the collimator, and hardware algorithm integration is also not needed. The difficulty of developing the software on the reconstruction machine is easier and simpler than implementing of a dynamic tracking algorithm on the hardware, the system is also easy to debug, and the probability of errors can be greatly reduced.

The invention discloses an adaptive hardware PID controller for controlling a motor and a control method of the adaptive hardware PID controller. The adaptive hardware PID controller comprises a first adder, a PID coefficient adjustment step length determining circuit, an adder group, a multiplier group and a second adder. The method comprises the following steps of subtracting a measured value from a target value; determining three coefficient adjustment step lengths according to the error magnitude and three coefficient adjustment step lengths of the previous period; adding the determined three coefficient step lengths to three coefficients of the previous period separately to obtain three coefficients of the period; multiplying the obtained three coefficients of the period with the error, error and differential of the error; and carrying out integral operation on the product of an integral coefficient and the error and then adding the product of a proportion coefficient and the error and the product of the integral coefficient and the differential of the error to obtain a control value. The adaptive hardware PID controller is widely applicable to various motor control scenes; and the motor is more accurately controlled by adopting different coefficients at different stages, control on the motor is completed through a pure hardware algorithm and the calculation speed is very high.

The invention discloses a trusted network communication method and device based on a safety chip hardware algorithm module. The method comprises the following steps of when a system is started, constructing the trust chain of a current system from the beginning of power on; when the application program of the current system initiates service connection to the opposite end system of the current system, carrying out first integrity measurement on the application program based on a whitelist mechanism, and according to a first integrity measurement result, determining whether the service connection is allowed to establish; and during a service connection maintenance process, carrying out a second integrity measurement on the application program based on the triggering of a predetermined instruction, and according to a second integrity measurement result, determining whether the service connection is continuously maintained. When the application program initiates the service connection tothe opposite end system, the first integrity measurement is performed, and during the service connection maintenance process, the second integrity measurement is performed so as to reduce a possibility that transmission data between a terminal system and a main station system is stolen, and improve the safety and the credibility of the method.

The invention provides an Ethernet controller security enhancement design method. An Ethernet controller performs the following operations in an encryption and decryption mode: carrying out control flow and data flow communication with an external host system through an AMBA bus interface module; realizing transmission of data used for access configuration of different buses in the sending and receiving directions through a DMA engine module; parsing and filtering Ethernet frame data in the sending and receiving directions through a protocol filtering and encapsulating module; sending link layer or network layer protocol data needing encryption and decryption to a data encryption and decryption module, and re-encapsulating the returned data; using a hardware algorithm to process the data through the data encryption and decryption module; sending and receiving data buffer through an MAC transaction module; and carrying out data communication with an external PHY chip through a PHY interface module.

The invention discloses a security network middleware for identity authentication, a method and apparatus for implementing the same. The middleware comprises an interface layer, a function layer and an engine layer. The interface layer is located on top of the function layer and is used for providing a channel for the client to call the middleware. The function layer is located on top of the engine layer, and is used for providing service interface to the interface layer, and is responsible for service realization of the middleware. The service includes signature, check mark, encryption and decryption. The engine layer comprises a national secret algorithm engine, an OpenSSL algorithm engine and a hardware algorithm engine. The middleware of the application is a front terminal of the authentication platform for collecting user information, which provides protection for safely collecting user identity information and avoids malicious use of the user identity information after the third-party network application collects the user identity information. At the same time, the user identity information is avoided to be stolen in the transmission process from the client to the authentication platform and from the authentication platform to the third-party network application.

The invention discloses a hardware algorithm model construction method based on SysML, and relates to the technical field of modeling simulation. The method comprises the following steps: establishinga module definition graph and an internal module graph of a hardware algorithm through SysML; storing the module definition graph and the internal module graph as a first text, and determining corresponding relationships between the module definition graph and the first text and between the internal module graph and the first text; extracting a first text by using a KMP algorithm and determininga mapping rule of the first text and the VHDL meta-model; and calling the VHDL meta-model, and converting the first text into a second text of the VHDL language according to the mapping rule. According to the method, the model is converted into the VHDL language for hardware algorithm model construction, the hardware modeling efficiency is improved, the problem that various models are difficult tounify in the complex product modeling process is solved, and the method is simple, convenient and easy to implement.

The invention provides a hanging type encryption algorithm engine system, which comprises a plurality of encryption algorithm nodes complying with a same interface definition and is characterized in that the algorithm nodes can be dynamically switched by a hanging type encryption algorithm engine; the hanging type encryption algorithm engine comprises a plurality of nodes of a uniform algorithm; and the encryption algorithm nodes are hung into the engine system through a uniform packaging interface. The hanging type encryption algorithm engine system has the beneficial effects that: 1) the resistance for bypass attack is combined with a traditional resisting mode and the effect is better; 2) the service quality of equipment is promoted, the continuous usage of the equipment is ensured, an average fault interval of the equipment is greatly increased, and the system diagnosis can be performed when the following system maintenance is carried out; 3) the developing efficiency is increased; and 4) the portability of a program is increased, and a new hardware algorithm node can be supported in the manner of slightly modifying and configuring an algorithm engine part.

The invention discloses a soft and hard synergic dynamic load storage method. The method comprises the steps of adopting a cold and hot tree in a data disk layout for recording disk strips, and dynamically allocating the disk strips. The energy is saved on the condition that the requirement for data transmission bandwidth is met, the xor computing part which is originally conducted through a CPU is achieved through an FPGA hardware algorithm, and the method is very suitable for a large-sized storage system for dynamic load change. According to the method, a novel disk layout mode is adopted and combined with hardware to be in charge of dynamic storage in the software and hardware combination mode, an opened disk is more reasonably utilized, the extra energy consumption brought by conversion of the disk is reduced, the address computing part is achieved through a software algorithm, the xor computing part is achieved through hardware, the disk energy consumption and the CPU resource when the data is stored are reduced, and the performance of an entire RAID storage framework is improved.