32 results about "Hardware algorithm" patented technology

The invention discloses a BIM-based electromechanical installation project progress planning and resource scheduling method and system, and belongs to the technical field of intelligent construction. The method comprises the following steps: 1) collecting multi-dimensional parameters (real-time construction parameters, prediction model parameters and external constraint parameters) in construction in a classified manner, and constructing a dynamic knowledge graph; 2) detecting progress and resource deviation based on a preset threshold value of the BIM model, and dynamically correcting a resource demand curve through the model; 3) in combination with constraint conditions such as policies and weather, optimizing an equipment scheduling path by adopting an algorithm, and screening compliance candidate schemes; 4) performing multi-objective optimization (minimizing progress deviation, maximizing resource utilization rate and controlling supply chain risk) on the scheme by using a genetic algorithm, and verifying through simulation iteration; and 5) outputting the optimal scheme and synchronizing the optimal scheme to a visual interface. According to the invention, real-time closed loop of data is realized through hardware-algorithm cooperation, and an efficient, dynamic and extensible intelligent management scheme is provided for electromechanical engineering.

The invention discloses an MVPS video coding method and device based on deep learning, and a medium, and relates to the technical field of video coding. The method comprises the following steps: acquiring a video stream, performing time domain and space domain feature extraction on the video stream through a feature extraction unit, and generating a joint feature map through an adaptive weight fusion layer; carrying out bidirectional feature interaction between hierarchies on the combined feature map to obtain a multi-scale feature set; generating a frame-level quantization parameter initial value according to the multi-scale feature set in combination with current network bandwidth feedback; performing time sequence consistency correction on the quantization parameter initial value to generate a target quantization parameter; and performing block coding on the current frame according to the target quantization parameter to generate a coded data stream. According to the method, through dynamic parameter adjustment, hardware algorithm collaborative optimization, cross-frame consistency enhancement and network awareness, the problems of low efficiency, insufficient real-time performance, unstable quality and poor adaptability of a traditional scheme are solved.

The invention discloses an edge real-time analysis-oriented sensing and calculation integrated spectrum camera processor system. Efficient edge calculation is realized through collaborative innovation of hardware, an algorithm and an accelerator. A hardware system adopts a three-level board card framework; a core board integrates a programmable logic unit and a processing system, and processes spectral data acquired by a CMOS board in real time; and the interface board accurately controls the power supply time sequence. In the lightweight classification network, the SSFE branch converts frequency domain filtering into cyclic matrix multiplication; carrying out normalization on the HFViT branch by using a batch normalization substitution layer; and an 8-bit full integer quantization strategy compression model is matched, and input spectrum identification characteristics are reserved. Time overlapping scheduling is designed for the accelerator, and SSFE matrix multiplication is executed in parallel in the HFViT calculation window period; the outer product pulsation architecture improves the matrix operation efficiency; and non-linear kernel multiplexing computing resources are unified. The system supports real-time classification of push-scan spectrum data, results are directly connected with sorting equipment, and the edge end embedded deployment requirement is met.

The invention relates to the technical field of power system safety monitoring equipment, in particular to an intelligent monitoring and early warning method, system and equipment for the icing thickness of a distribution line and a medium, and synchronous acquisition and preprocessing of multi-dimensional parameters are realized by deploying an ice-resistant packaging multi-parameter sensing array; dynamically optimizing a modal number and a penalty factor of variational modal decomposition by using a genetic algorithm to realize multi-scale feature decoupling of the icing signal; a gating circulation unit is adopted to extract time sequence features, the time sequence features are input into a Kolmophilov-Arnod network to execute nonlinear mapping, and dual-path output is fused through residual connection; deploying the trained hybrid model to an industrial-grade edge computing unit, and completing local real-time reasoning by using edge computing power; triggering incremental updating of the sliding window based on a prediction error threshold value, and dynamically adjusting the weight of an output layer to maintain the adaptability of the model; through hardware-algorithm collaborative innovation, reliable operation is guaranteed in an extremely low-temperature environment, the early warning response time is remarkably shortened, and the prediction precision is improved.

The present invention belongs to the field of network security application scenarios and relates to a high-speed query method for a firewall session link table based on a hardware HASH algorithm. A high-speed query method for a firewall session link table based on a hardware HASH algorithm is characterized in that it includes a five-tuple, wherein the five-tuple includes a source IP, a source port, a destination IP, a destination port, and a protocol number, and a HASH algorithm is performed on the five-tuple. Through the HASH algorithm of the present application, session link table conflicts can be greatly reduced and the efficiency of link table queries can be improved. A HASH index allocation method based on the HASH algorithm reasonably distributes a large number of session link tables in a hardware memory, facilitates the query of the session connection table, and ensures that the firewall device can establish up to 1 million session links.

1. The name of the design product: combined medical AI computing power all-in-one machine. 2. The use of the design product: intelligent equipment for integrating computing power hardware, AI algorithms, and medical application systems. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view.

The invention discloses a power management system adapted to an extremely low temperature environment. Through a multi-level self-adaptive heating mechanism and a hardware-algorithm cooperative control strategy, stable operation in an extremely low temperature environment is realized. The power manager integrates a closed-loop temperature control system and double-order starting logic of'hardware priority-software takeover ', the special charger adopts a distributed temperature sensing and space temperature field reconstruction technology, reliable charging and discharging management under the extreme environment of-68 DEG C is achieved through cooperation of the closed-loop temperature control system and the space temperature field reconstruction technology, heating extra power consumption is reduced by 90% or above, and the maximum temperature difference of a battery bin is smaller than or equal to 2 DEG C; and the cold start success rate is 100%. The power supply system can be widely applied to extremely-low-temperature individual power supply systems, extremely-low-temperature battery packs and other scenes, and the core technical bottleneck of the power supply system in an extreme environment is solved.

Technologies for compilers that implement non-power of two Fast Fourier Transform (FFT) algorithms are described. The non-power of two FFT algorithm uses a recursive function to generate a hardware design of a set of compute blocks of a fixed-point digital signal processor (DSP) and routing data between the compute blocks. The compiler receives input specifying a sequence of indexes and a bit width of the fixed-point DSP and performs a process. The process splits the sequence using a recursive loop, determines a number of multiplications in the hardware design, and generates a trace graph of the non-power of two FFT algorithm. The process is entered via the recursive function and exists when the recursive loop decrements to a specified value corresponding to a Radix-3 or Radix-2. The compiler outputs data, including the hardware design, the number of multiplications in the hardware design, and the trace graph.

The application discloses a sensing and computing integrated spectral camera processor system for edge real-time analysis, and realizes efficient edge computing through hardware-algorithm-accelerator collaborative innovation. The hardware system adopts a three-level board card architecture: the core board integrates a programmable logic unit and a processing system, and real-time processing of spectral data collected by a CMOS board; the interface board accurately controls power timing. In the lightweight classification network, the SSFE branch converts frequency domain filtering into cyclic matrix multiplication; the HFViT branch replaces layer normalization with batch normalization; cooperate with 8-bit full integer quantization strategy to compress the model and reserve the input spectral discrimination features. The accelerator designs time overlap scheduling, and executes SSFE matrix multiplication in the HFViT calculation window period; the outer product pulsation architecture improves the matrix operation efficiency; and unified nonlinear kernel multiplexing calculation resources. The system supports real-time classification of push-broom spectral data, and the results are directly connected to the sorting equipment, and meets the needs of edge embedded deployment.

The invention is suitable for the technical field of intelligent terminals, and provides a display image quality evaluation method and device, terminal equipment and a storage medium, and the method comprises the steps: obtaining first image data representing the original state of the image quality of a source end in a display link, the second image data represents an image quality intermediate state after being processed by a processor hardware algorithm in the display link and before electro-optical conversion; obtaining electro-optical characteristic data of a display terminal in the display link; respectively converting the first image data and the second image data into a linear color space based on the electro-optical characteristic data to obtain first linear color image data and second linear color image data; and evaluating the image quality change of the display link according to the first linear color image data and the second linear color image data. According to the method and the device, the image quality change in the display link can be comprehensively and accurately evaluated.

The invention discloses a construction method and system of a role IP enabling linkage control model, the system comprises a sensor array module, a GPU-CPU heterogeneous computing system and an infrared eye movement tracking module as a physical feedback module, and the sensor array module collects multi-modal biological and behavior data from a performer through a fixed physical layout; according to the heterogeneous computing system, through hardware algorithm distribution, a GPU is used for executing a geometric deep learning network, and a CPU is used for executing a recurrent neural network so as to efficiently process data and fuse the data into a unified role IP state vector; and the physical feedback module carries out closed-loop online optimization on a state vector generation strategy by capturing eye movement data of a terminal observer as a reward signal of a reinforcement learning algorithm. Through a specific hardware closed-loop system, the adaptive cost is greatly reduced, and meanwhile, the IP expressive force and the audience immersion degree generate nonlinear technical effect jump.

The invention relates to the technical field of new energy automobile battery teaching, and discloses a full-link virtual-real linkage battery simulation teaching system, which comprises hardware simulation, 3D / VR simulation software and an algorithm verification and fault simulation module, and is characterized in that the hardware simulation module comprises a modular insulation rack, a high-precision battery simulator, a waterway heat dissipation system and VR interaction equipment; equipment interconnection is realized through the communication module; the 3D / VR module supports 3D dynamic display and immersive operation simulation of the battery pack; the fault simulation module can issue a fault signal and is linked with hardware; the algorithm verification module supports fault data injection and user-defined algorithm operation; the system collects hardware data through the BMS controller and transmits the hardware data to the software system through the communication module, virtual and real data synchronization and a whole-process teaching closed loop are achieved, practical training safety, practical operation authenticity and teaching depth are considered, and the system is suitable for multi-scene battery teaching.

The invention discloses a dynamic range compression image enhancement algorithm for an ultrahigh-resolution high-dynamic image and hardware thereof, and the algorithm comprises the steps of RGB-XYZ color space conversion, n-frame average maximum brightness statistics, adaptive brightness zooming, dynamic mapping factor calculation, segmented low-bit mapping and the like, and achieves high-dynamic range precise compression. Hardware adopts a modular design, and ASIC / FPGA deployment is supported. According to the method, the dynamic range compression from the high-bit high-dynamic image to 8-bit display is efficiently completed, the details of a dark part and a medium-brightness region are reserved to the maximum extent, and the visual effect of an original scene is restored; a traditional high-complexity algorithm is abandoned, the calculation amount and the on-chip storage cost are reduced by simplifying the design, and low-time-delay and low-power-consumption deployment is achieved; and adaptive parameters and dynamic mapping are adopted, so that the problems of overexposure and underexposure caused by a fixed mapping curve are avoided, the quality of a reconstructed image is remarkably improved, and the high-quality display requirement in a low-delay and low-power-consumption scene is perfectly met.

The invention relates to the technical field of numerical calculation and hardware algorithm implementation, in particular to a segmentation strategy-based high-precision logarithmic function implementation method, which comprises the following steps of: carrying out standardization processing on an input floating-point number, generating a threshold signal for path selection based on a relationship between an index and a mantissa of the floating-point number, and then, carrying out segmentation on the threshold signal; performing sub-interval division on the standardized data, determining corresponding sub-interval numbers, selecting a sub-interval starting point as a polynomial approximation reference point, generating parameter data for polynomial calculation and third-order Taylor expansion calculation, performing numerical format unification and shift alignment processing on the parameter data, and then obtaining a polynomial approximation reference point; the method comprises the following steps: respectively performing polynomial calculation and Taylor expansion calculation to obtain a polynomial fixed-point result and a Taylor expansion temporary result, performing normalization and rounding processing on calculation results to ensure that output meets floating point format requirements, and finally realizing path selection according to a threshold signal and outputting a final logarithmic function result. Therefore, the calculation precision and the operation efficiency are effectively considered.

The invention provides an acceleration system and method of a random Fourier feature learning algorithm, relates to the technical field of hardware acceleration of the random Fourier feature learning algorithm, and realizes hardware native calculation of a random Fourier feature kernel function through light wave interference. Mathematical mapping and complex operation are converted into a continuous physical process of optical phase modulation and interference, and the analog-to-digital conversion and digital operation overhead of a traditional electronic architecture is reduced. The dynamic reconfigurable light modulation unit is combined with a wavelength multiplexing technology, supports real-time adjustment and multi-probability distribution switching of RFF kernel function parameters, and flexibly adapts to diversified data characteristics and task requirements. The system-level photoelectric hybrid interconnection and multi-modal scheduling mechanism realizes hierarchical expansion from vector inner product to matrix operation, an attention mechanism and a Transform model, and considers edge end low-power-consumption reasoning and a data center-level training scene. The anti-interference characteristic of optical calculation and the hardware-algorithm closed-loop calibration design guarantee the calculation precision and reliability in a complex environment.

The invention relates to the technical field of integrated circuit design, and particularly discloses a device and method for accelerating high-precision ADC data operation, and the device comprises a bus which comprises an address bus and a data bus; the hardware algorithm accelerator comprises an address mapping logic module, an input and output mapping module, a register module and an algorithm acceleration core function module; the address mapping logic module is used for splitting an address access request from an address bus into a read-write access command of the register module and a parameter and operation command of the algorithm acceleration core function module; the register module includes a configuration register, a plurality of operand registers, and a configuration register. According to the method and the device, the address access request from the address bus is divided into two parts, meanwhile, calculation input and output are selected through address mapping, a calculation result can be directly imported into a newly-initiated calculation input end, read-write of a processor to an operand register can be reduced, and the calculation efficiency is improved.

A storage device may include an external NAND control (ENC) circuit and a nonvolatile memory device. The ENC circuit may include a deserializer configured to deserialize data received from an external device, a buffer memory configured to store the data, and a data loader configured to generate a control signal based on the data. The nonvolatile memory device may include a memory cell array, a voltage generator, a row decoder, and a page buffer. The data may include control information associated with implementing a hardware algorithm.

The invention provides a laser wavelength stabilizing device and method based on a special TEC controller. The device comprises a core chip module, a temperature setting module, a temperature feedback module, a TEC load module, a power supply and protection module and a PID compensation module, wherein the core chip module adopts an ADN8834 or ADN8835 chip to construct a hardware PID closed-loop control architecture; the method comprises the steps that a target temperature voltage signal is output through the temperature setting module, the temperature feedback module collects the temperature of the laser in real time and converts the temperature into feedback voltage, the core chip module compares the target signal with the feedback signal based on a hardware PID algorithm, a regulation and control current is output to drive the TEC load module to achieve refrigeration / heating, and control performance is optimized in cooperation with the PID compensation module. The invention is applied to the technical field of laser temperature control and wavelength calibration.

This invention discloses a target tracking test method for wireless detection devices based on multi-dimensional dynamic scenarios, belonging to the interdisciplinary field of target detection and artificial intelligence. The method includes: Step 1, generating a high-fidelity target tracking dynamic scenario through hierarchical modeling; Step 2, generating structured test data based on a parameterized space; Step 3, performing multi-dimensional performance evaluation on a verification platform: inputting the generated I / Q data into the algorithm under test deployed on the platform, and calculating five types of indicators in real time; Step 4, dynamically optimizing the test scenario based on the evaluation results. This invention addresses the shortcomings of existing technologies in dynamic scenario reproduction, algorithm evaluation dimensions, and hardware-in-the-loop verification by constructing a configurable electromagnetic environment model, a multi-dimensional evaluation indicator system, and a hardware-in-the-loop verification architecture, thereby quantitatively evaluating the real-world capabilities of algorithms in complex dynamic environments.

The invention discloses an MLC controller based on a hardware PID algorithm and a control method thereof, the MLC controller comprises an FPGA control module, the FPGA control module integration comprises a parallel hardware PID controller array, the parallel hardware PID controller array is composed of N independent hardware PID controllers, each hardware PID controller correspondingly controls one leaf of a multi-leaf collimator, N is a positive integer greater than 1, and the FPGA control module integration comprises an FPGA control module, the encoder interface array is used for reading position encoder data of N blades of the multi-blade collimator in parallel and sending the position encoder data to the corresponding hardware PID controllers; the PWM signal generation module array is used for generating N paths of PWM signals to drive corresponding blade motors according to the control signals output by the parallel hardware PID controller array; the data cache analysis module is used for receiving a target track instruction of an upper computer and sending a parameter instruction to the parallel hardware PID controller array; wherein each hardware PID controller in the parallel hardware PID controller array independently runs in parallel based on a global clock signal.

The application relates to the technical field of integrated circuit design, and particularly discloses an apparatus and method for accelerating high-precision ADC data operation, which comprises a bus including an address bus and a data bus; a hardware algorithm accelerator including an address mapping logic module, an input-output mapping module, a register module and an algorithm acceleration core function module; the address mapping logic module is used for splitting an address access request from the address bus into two parts of a read-write access command of the register module and parameters and operation commands of the algorithm acceleration core function module; and the register module comprises a configuration register, a plurality of operand registers and the configuration register. According to the application, the address access request from the address bus is split into two parts, the calculation input and output are selected through address mapping, the calculation result can be directly introduced into a newly initiated calculation input end, the read-write of the operand register by the processor can be reduced, and the operation efficiency is improved.

The invention discloses a cross-module parallel high-speed space-time anti-interference hardware algorithm. According to the method, a space-time anti-interference algorithm is decomposed into an autocorrelation matrix solving module, a Corisky decomposition module and a weight calculation module, and cross-module parallel calculation of the three modules is realized by means of an FPGA by optimizing a calculation sequence of the three modules on matrix elements and a matrix storage mode; the system calculation speed under the conditions of high array element number and delay tap number is obviously improved; through parallel RAM storage of columns of the middle matrix, extra time overhead caused by serial memory access of a large number of matrix elements is avoided; by reasonably designing a calculation sequence in each module, highly parallel calculation in the modules is realized; all modules are uniformly planned to perform calculation according to a column parallel mode, cross-module parallel calculation of the three modules is realized by means of column index transmission among the modules, and the calculation delay of the whole algorithm is remarkably reduced; the method is suitable for high-speed anti-interference demand scenes such as satellite communication and satellite navigation.

The invention discloses an intelligent detection, identification and tracking system and method based on a domestic micro-processing platform, and belongs to the technical field of embedded artificial intelligence and computer vision. The system adopts a chip of National Coriolis Microelectronics 7608 as a core, and combines a lightweight detection model, a high-precision identification network and a fusion tracking algorithm; through dynamic memory allocation, mixed precision reasoning and a self-adaptive tracking mechanism, the 25FPS processing capability under the resolution of 1080p is realized, the end-to-end delay is lower than 50ms, and the power consumption is lower than 3W. According to the system, low-power-consumption and high-precision end-side intelligent processing is realized through hardware-algorithm collaborative optimization, and the system is suitable for scenes of security monitoring, intelligent transportation, industrial automation and the like.

The invention provides a compensation circuit and a compensation method for a radio frequency clock chip, and the method comprises the steps: firstly, collecting a real-time temperature value, a power noise condition and other chip working environments; secondly, based on a preset frequency deviation curve, according to the real-time temperature value, generating a first compensation voltage of the voltage-controlled oscillator by adopting an interpolation algorithm; then, based on a preset spectral analysis algorithm, high-frequency noise and low-frequency noise in the power supply noise are separated, and the power supply noise is suppressed in combination with a feedback control algorithm and cascade filter network frequency division; and finally, on the basis of the difference value between the output frequency of the voltage-controlled oscillator and the target frequency, generating a second compensation voltage of the voltage-controlled oscillator on the basis of a preset nonlinear tuning characteristic curve. According to the invention, a multi-dimensional cooperative compensation mechanism is formed through a hardware-algorithm, the problem of frequency stability of the radio frequency clock chip in a complex environment is solved, and the comprehensive performance of the radio frequency clock chip is improved to a new dimension.

The invention discloses an FPGA-based underwater target recognition convolutional neural network acceleration method, and aims to solve the problem that a convolutional neural network in underwater edge equipment is dense in calculation and limited in storage. A lightweight network formed by three layers of depth separable convolution and two layers of full connection layers is designed, parameter lightweight is realized through a batch normalization parameter fusion formula and is converted into a semi-precision floating point format, and an acceleration circuit for deep convolution block calculation and full connection layer merging IP core packaging is designed based on an FPGA. And parallel strategies such as loop expansion and pipeline optimization are combined to improve the calculation efficiency. The innovation points to be protected are a collaborative application method of deep separable convolution and parameter lightweight processing, a circuit design strategy of realizing convolution layer block calculation and full connection layer combination by the FPGA, and a parallel optimization strategy combination of loop expansion and array segmentation. And low-power-consumption real-time reasoning of underwater target recognition is realized through collaborative design of a hardware algorithm.

The invention relates to the technical field of motor control, in particular to a three-phase six-wire motor controller, which comprises an independently researched and developed motor driving chip P2850, a power supply module, a sensor group, a communication interface, a driving circuit, a power module and a heat dissipation system. The P2850 chip integrates a special hardware accelerator and an MCU core, executes a hardware FOC algorithm, and accurately regulates and controls six-path phase current in real time; according to the power module, 12 power semiconductor switching devices form two independent three-phase full-bridge inverter circuits. By the adoption of the technical scheme, high-order harmonic current can be effectively restrained, the operation efficiency of the motor is improved, vibration noise is reduced, the torque output and speed regulation range is widened, and the system reliability and the fault-tolerant capability are enhanced.

The invention provides a side channel attack resistant post-quantum cryptographic algorithm security implementation method and system, and belongs to the technical field of cryptographic hardware security. In password hardware, a hardware-algorithm collaborative abstraction layer is used as a core control hub, and the method comprises the following steps of: constructing a logically isolated security execution environment supported by protected hardware; loading a security algorithm image subjected to side channel reconstruction resistance; in the process of executing the algorithm mapping, the abstraction layer dynamically schedules hardware resources and synchronously injects randomized disturbance; meanwhile, physical side channel signals are collected in real time through a safety monitoring unit; and when the signal is judged to be abnormal, feeding back to the abstraction layer to dynamically adjust a disturbance strategy or switch a standby execution path. Through cooperation and dynamic adjustment of software and hardware resources, the problems of protection design lagging, resource static splitting and lack of adaptive ability in the prior art are solved, efficient active security defense is achieved, and the protection ability of post quantum cryptography hardware for resisting side channel attacks is improved.

The application discloses a kind of supporting password card algorithm library operation implementation method and related device, algorithm library has software algorithm interface and hardware algorithm interface, algorithm library calls software algorithm interface and / or hardware algorithm interface to complete preset operation task, wherein: software algorithm interface is connected with server signal, to realize preset operation task in server by preset algorithm;Hardware algorithm interface is connected with password card signal, to realize preset operation task in password card by preset algorithm;Software algorithm interface and hardware algorithm interface are compatible with each other.Compared with prior art, by setting software algorithm interface and hardware algorithm interface in algorithm library simultaneously in the application, user can select suitable use mode according to actual demand, and software algorithm interface and hardware algorithm interface are compatible with each other, software algorithm interface and hardware algorithm interface can cooperate to share load, deployment cost is low, and it is more flexible and convenient to deploy.

The invention discloses a damaged pulse restoration method based on deconvolution abnormal value elimination, and relates to the technical field of pulse restoration, and the method comprises the following steps: S1, obtaining an original pulse data sequence; s2, obtaining a damaged pulse identification result according to the original pulse data sequence; and S3, based on the damaged pulse identification result, completing damaged pulse repair. Compared with a traditional trapezoid forming hardware algorithm, the cascade structure design is adopted, only the pulse recognition algorithm, the baseline selector and the repair selector are added, and the algorithm is easy to achieve in hardware such as an FPGA.

The application discloses a multi-interface compatible SM3 / SM4 algorithm hardware module instruction translation method and related devices, including a host end, a translation chip end and a hardware algorithm end, wherein the host end and the translation chip end interact information, and the translation chip end and the hardware algorithm end interact information, the method and related devices have the characteristics of strong hardware form compatibility, high interface protocol adaptability and low calling complexity.