High-speed parallel processing architecture for data center

A parallel processing, high-speed serial interface technology, applied in the field of data processing, can solve the problems of loss of important information and discontinuity of vibration data collection, and achieve the effect of improving processing capacity and reducing system scheduling delay.

Active Publication Date: 2015-11-11
厦门中源能链科技有限公司
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Problems solved by technology

[0008] The present invention provides a high-speed parallel processing architecture of a data center, which solves the technical problem of discontinuity in vibration data collection in the prior art, resulting in loss of important information

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Embodiment Construction

[0014] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0015] Such as figure 1 As shown, it is a schematic structural diagram of a high-speed parallel processing architecture of a data center provided by an embodiment of the present invention, including multiple processing single boards, and one processing single board includes: at least two transceivers, at least one FPGA programmable logic chip and At least two processor CPUs, the CPUs are connected with the FPGA chip through the CPU high-speed serial interface, and the FPGA chip is internally provided with a plurality of high-speed serial transceiver cores and corresponding coprocessor MCUs; A plurality of embedded memories corresponding to each coprocessor MCU are embedded; the embedded memories are configured in a dual-port mode ...

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Abstract

The present invention relates to the field of data processing, and discloses a high-speed parallel processing architecture for a data center. The high-speed parallel processing architecture comprises a plurality of processing boards, and is characterized in that each processing board comprises at least two transceivers, at least one FPGA programmable logic chip and at least two processors (CPUs), wherein the CPUs are connected with with the FPGA chip through CPU high-speed serial interfaces; and a plurality of high-speed serial transceiver cores and a plurality of corresponding coprocessors (MCUs) are arranged in the FPGA chip; a plurality of embedded memories corresponding to each coprocessor MCU are embedded into the FPGA ; and each embedded memory is configured to be in a dual-port mode capable of reading and writing. According to the high-speed parallel processing architecture, an embedded CPU+FPGA architecture is realized; high-speed parallel hardware algorithms are realized, so that processing ability of basic computing elements is greatly improved, and system schedule delay is reduced.

Description

technical field [0001] The invention relates to the field of data processing, in particular to a high-speed parallel processing architecture of a data center. Background technique [0002] With the rapid development of information technology, the term "Energy Internet" has swept the energy circle since 2014. Technologies such as the Internet of Things, big data, and intelligence have been gradually applied to the traditional energy industry. With the four advantages of “Scale” and big data, cloud computing and other Internet technologies are used to build an energy-saving monitoring and energy management platform to realize intelligent and dynamic deployment of energy production, transmission and consumption, so as to improve efficiency, save energy and reduce emissions. The general trend. At present, energy-saving monitoring and energy management platforms usually adopt a three-layer structure, the bottom layer is metering instruments, sensors or actuators; the second laye...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/163G06F15/173
Inventor 林雪山
Owner 厦门中源能链科技有限公司
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