66 results about "Parallel processing architecture" patented technology

A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.

The present invention relates to a robot hybrid system application framework based on a multi-core processor architecture. In the robot system with ARM/X86 multi-core processor as the controller, multi-core parallel processing architecture of the ARM/X86 multi-core processor is used to run the robotic hybrid system application framework comprising real-time operating system, non-real-time operating system and system supporting frame in the whole robot controller, so as to provide improved operating system services. In this application framework, a real-time operating system runs independently in one ARM/X86 core, while several non-real-time operating systems run on other ARM/X86 cores. The operating systems occupy processor resources and peripherals separately and run robotic applications with different real-time requirements. The application program can be used as a unified robot operating system (ROS) application node.

A full width array CCD sensor is incorporated in the media path to monitor fused pages by calculating area coverage from multiple engines in a Tightly Integrated Parallel Process (TIPP) architecture. With knowledge of the area coverage differences between print engines for a given pixel count to the ROS, a relative density difference of each engine is determined. Based on the determined relative density difference, an adjustment is calculated and applied to the engine with the largest error to match the area coverage(s) of the other engine(s).

A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

A parallel processing architecture for a relational database management system (RDBMS) that supports both a process model operating system and a thread model operating system. The RDBMS is implemented as a shared nothing, single database image utilizing Parallel Database Extensions (PDEs) that insulate the RDBMS from the specifics of the operating system and that provide the necessary techniques for accessing common memory segments.

Apparatuses and methods are disclosed that create a synthetic fovea in order to identify and highlight interesting portions of an image for further processing and rapid response. Synthetic foveal imaging implements a parallel processing architecture that uses reprogrammable logic to implement embedded, distributed, real-time foveal image processing from different sensor types while simultaneously allowing for lossless storage and retrieval of raw image data. Real-time, distributed, adaptive processing of multi-tap image sensors with coordinated processing hardware used for each output tap is enabled. In mosaic focal planes, a parallel-processing network can be implemented that treats the mosaic focal plane as a single ensemble rather than a set of isolated sensors. Various applications are enabled for imaging and robotic vision where processing and responding to enormous amounts of data quickly and efficiently is important.

The invention relates to a TMIS traffic flow determination method and system based on cloud computing. The TMIS traffic flow determination method comprises the steps of (1) constructing a distributed storage resource pool on the basis of a cloud platform, collecting and storing monitoring data related to traffic flow calculation through a TMIS, (2) preprocessing the collected monitoring data through a concurrent processing framework, (3) writing a traffic flow calculation algorithm under the concurrent processing framework, utilizing static data for calculating the result of long-term traffic flow calculation, (4) utilizing the static data and dynamic data under the distributed environment for calculating the result of real-time traffic flow calculation corresponding to each station, and (5) providing a traffic flow calculation inquiry service externally through the cloud platform. The TMIS traffic flow determination system comprises a collecting layer, a storage layer, an engine layer, a service layer and a web service layer. According to the TMIS traffic flow determination method and system based on cloud computing, the cloud platform is utilized for obtaining various data required by traffic flow calculation in the TMIS, the concurrent computation is utilized for rapid data processing, and long-term and real-time traffic flow calculation and determination of railway transportation can be achieved.

The invention discloses a full coherence accumulation time-frequency domain parallel capturing method based on FFT, in order to quickly capture a burst direct sequence spread spectrum signal with low signal to noise ratio and large frequency offset. The full coherence accumulation time-frequency domain parallel capturing method disclosed by the invention comprises two realization parts: pseudo code correlation based on FFT and full coherence accumulation based on FFT. Two methods of symbol correlation and zero complement FFT are used for further reducing the sinc loss in a pseudo code correlation process and the scallop loss in an accumulation process. The parallel capturing method is used for reducing the consumption of processing resources by the buffer of a large amount of intermediate data information and a parallel processing architecture based on FFT, obtaining a very high signal to noise ratio of a correlation peak within a short time, precisely evaluating Doppler frequency offset in a parallel search process of a pseudo code phase and reducing the average capturing time.

Techniques are disclosed for creating a background model of a scene using both a pixel based approach and a context based approach. The combined approach provides an effective technique for segmenting scene foreground from background in frames of a video stream. Further, this approach can scale to process large numbers of camera feeds simultaneously, e.g., using parallel processing architectures, while still generating an accurate background model. Further, using both a pixel based approach and context based approach ensures that the video analytics system can effectively and efficiently respond to changes in a scene, without overly increasing computational complexity. In addition, techniques are disclosed for updating the background model, from frame-to-frame, by absorbing foreground pixels into the background model via an absorption window, and dynamically updating background/foreground thresholds.

A UAV has two rotors. First and second sensors sense a first and second type of input respectively. The second type of input is different than the first type, the first sensor providing a first sensor output and the second sensor providing a second sensor output. The first sensor output is input to a first computer and the second sensor output is input to a second computer. The first and second computer communicate in parallel to process the first and second sensor outputs to create a control signal having a predetermined number of variables therein, each variable having an exclusive position within the signal. The first computer outputs a first variable and the second computer outputs a second variable, each output being assigned an exclusive position within the control signal. At least one of the first and second computers outputting the control signal to the rotors.

Present invention unity parallel processing systems and methods facilitate flexible utilization of sequential program applications in a distributed multi-computer parallel processing environment. The new unity parallel processing architecture enables multiple processing nodes (e.g., SMPs) to perform multi-thread processing within the multiple processing nodes while providing a shared virtual global memory space. Symmetric multiprocessors run shared memory applications with modified runtime guidance directives that permit the memories to emulate a virtual global memory across the plurality of symmetric multiprocessors. Within each SMP node, programs utilize multiple threads according to directives and library calls. Across multiple SMP nodes, each SMP node is treated as a single process with one-way communication to other SMP nodes. Portions of the program data are stored in memories associated with the SMP nodes and communication of the program data across multiple SMP nodes is controlled by unity compiler directives.

The present invention provides for a type of parallel processing architecture in which a plurality of processors has access to a shared memory hierarchy level. A memory hierarchy level has a coherence directory and associated directory data with a plurality of cachelines each associated with different data. Prefetch caches are interconnected to processor memory and a plurality of processor elements, each element interconnected to different buffers. Cache lines are requested from memory, and the requests, responses, and detections therein are available for particular access modes, therein providing additional coherence of the data. Processing of said directory data is performed by processing elements. In one embodiment, the system comprises an integrated prefetch cache.

The invention discloses a sub-band-processing-based clutter suppression method and apparatus for a passive radar. The method comprises the four steps of sub band decomposition, over-sampling clutter sub space construction, LS adaptive filtering, and sub band synthesis. To be specific, a monitoring signal is composed into multi-path sub band signals; a clutter sub space is constructed in an over sampling mode by using a reference signal; sub band decomposition is carried out; LS adaptive filtering is carried out on each sub band; and then the filtered sub band signals are synthesized to obtain a monitoring signal after clutter suppression. According to the method, the robustness on non-ideal factors like a carrier frequency offset, a sampling rate frequency offset, a fractional delay, and a channel frequency response and the like is high; the clutter suppression performance is close to the theoretical upper limit; the calculation load is low; the parallel processing architecture is provided; and thus the method and apparatus are suitable for engineering real-time implementation and have the popularization and application values.

A parallel processing architecture of flash memory and method thereof are described. A processing unit classifies a plurality of commands to generate a first command group and a second command group respectively. The processing unit executes the first command group and the second command group. A first control unit performs the first command group to access the data stored in the first memory unit, and a second control unit simultaneously performs the second command group to access the data stored in the second memory unit for processing the data stored in the first and the second memory units in parallel.

Techniques are disclosed for creating a background model of a scene using both a pixel based approach and a context based approach. The combined approach provides an effective technique for segmenting scene foreground from background in frames of a video stream. Further, this approach can scale to process large numbers of camera feeds simultaneously, e.g., using parallel processing architectures, while still generating an accurate background model. Further, using both a pixel based approach and context based approach ensures that the video analytics system can effectively and efficiently respond to changes in a scene, without overly increasing computational complexity. In addition, techniques are disclosed for updating the background model, from frame-to-frame, by absorbing foreground pixels into the background model via an absorption window, and dynamically updating background/foreground thresholds.

The invention discloses a mobile payment smart card. The mobile payment smart card is integrated with a main control communication smart card chip and a financial smart card chip with payment function in an SIP mode, wherein the main control chip is communicated with a mobile phone or other external equipment and performs access control on an affiliated payment smart card chip. The mobile paymentsmart card has contact and non-contact functions, the contact function is controlled by the main control chip, and the non-contact function is controlled by the financial smart card chip. The main control chip is a high-capacity soft mask chip and can support changeful communication application requirements, and the access control of the main control chip on the affiliated payment chip enables the mobile payment smart card to realize STK extension such as financial account information search, aerial earmark and the like by the telecommunication function provided by the main control chip. The affiliated payment chip independent from the main control chip executes the non-contact function, and the mobile payment smart card has higher comprehensive stability due to a parallel processing architecture of the two chips; and the physical independence of the affiliated payment chip ensures that the data has high security of financial level.

The present invention provides for a type of parallel processing architecture in which a plurality of processors has access to a shared memory hierarchy level. A memory hierarchy level has a coherence directory and associated directory data with a plurality of cachelines each associated with different data. Buffers are interconnected to processor memory and a plurality of processor elements, each element interconnected to different buffers. Cache lines are requested from memory, and the requests, responses, and detections therein are available for particular access modes, therein providing additional coherence of the data. Processing of the directory data is performed by processing elements.

A three-dimensional VLSI integrated circuit apparatus is disclosed having a plurality of VLSI layers. A first VLSI layer includes a first silicon sublayer coupleable to at least one heat sink, and a first active silicon sublayer having a (first) plurality of photonic receivers (or transceivers); and a second VLSI layer including a second silicon sublayer having a first plurality of microfluidic cooling channels, and a second active silicon sublayer of the plurality of second VLSI sublayers having an interconnection network. Additional VLSI layers may also include a third VLSI layer having a third silicon sublayer having a second plurality of microfluidic cooling channels and a third active silicon sublayer having a (second) plurality of photonic transmitters (or transceivers). Additional VLSI layers may also include a third VLSI layer having microfluidic cooling channels and memory circuits, and a fourth VLSI layer having microfluidic cooling channels and parallel processing circuitry.