Hardware algorithm model construction method based on SysML

A hardware algorithm and construction method technology, applied in special data processing applications, CAD circuit design, etc., can solve problems such as difficult model unification, and achieve the effect of improving efficiency and simple and easy implementation

Active Publication Date: 2021-02-23
BEIJING INFORMATION SCI & TECH UNIV
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  • Abstract
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Problems solved by technology

[0004] In view of this, the present invention provides a hardware algorithm model construction method based on SysML to solve the problem that various models are diffic

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  • Hardware algorithm model construction method based on SysML
  • Hardware algorithm model construction method based on SysML
  • Hardware algorithm model construction method based on SysML

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Embodiment Construction

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0030] The embodiment of the present invention discloses a method for constructing a hardware algorithm model based on SysML, and the specific steps include the following:

[0031] Step 1: Establish the module definition diagram and internal module diagram of the hardware algorithm through SysML;

[0032] The module definition diagram gives the names, types, and associations of each module of the model, indicating the entities and modules in the hardware circu...

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Abstract

The invention discloses a hardware algorithm model construction method based on SysML, and relates to the technical field of modeling simulation. The method comprises the following steps: establishinga module definition graph and an internal module graph of a hardware algorithm through SysML; storing the module definition graph and the internal module graph as a first text, and determining corresponding relationships between the module definition graph and the first text and between the internal module graph and the first text; extracting a first text by using a KMP algorithm and determininga mapping rule of the first text and the VHDL meta-model; and calling the VHDL meta-model, and converting the first text into a second text of the VHDL language according to the mapping rule. According to the method, the model is converted into the VHDL language for hardware algorithm model construction, the hardware modeling efficiency is improved, the problem that various models are difficult tounify in the complex product modeling process is solved, and the method is simple, convenient and easy to implement.

Description

technical field [0001] The invention relates to the technical field of modeling and simulation, and more specifically relates to a method for constructing a hardware algorithm model based on SysML. Background technique [0002] In the process of building the hardware circuit model, VHDL is generally used to describe the digital circuit logic. Ultra-high-speed integrated circuit hardware description language was born in 1982. It was originally a hardware description language proposed by the U.S. Department of Defense for its ultra-high-speed integrated circuit research program. Others can easily understand the design of the circuit. However, the VHDL syntax is complicated and difficult to understand, and it needs professionals with relevant experience in circuit design to design. However, for the hardware kernelization requirements of complex algorithms, many algorithm professionals do not understand VHDL, and hardware professionals do not understand algorithms. [0003] W...

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Application Information

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IPC IPC(8): G06F30/33
CPCG06F30/33
Inventor 刘越赵淳
Owner BEIJING INFORMATION SCI & TECH UNIV
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