Method for fabricating patterns on a wafer through an exposure process

A chip and pattern technology, applied in the photolithographic process of the pattern surface, semiconductor/solid-state device manufacturing, optics, etc., can solve problems such as storage node 61 shape defects

Inactive Publication Date: 2010-11-03
SK HYNIX INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The storage node 61 is formed in a columnar shape with a very large height compared to the bottom area to increase the effective area of ​​the dielectric layer, and therefore, a slight pattern defect generated in the exposure process may cause a serious defect in the shape of the storage node 61
[0009] As described above, since the pattern transfer performed by exposure on the partial field region 33 has many defect factors (including storage node defects 63, 65, and 67), it is desirable to develop a pattern transfer method in the partial field region 33. A method of integrating a semiconductor device, the generation of pattern defects is limited in the partial field region 33

Method used

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  • Method for fabricating patterns on a wafer through an exposure process
  • Method for fabricating patterns on a wafer through an exposure process
  • Method for fabricating patterns on a wafer through an exposure process

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Embodiment Construction

[0034] Hereinafter, a method for manufacturing a photomask will be described in detail with reference to the accompanying drawings.

[0035]In the disclosed technique, pattern transfer is performed by exposing exposure irradiation on a partial field in an edge region of a wafer using a photomask, wherein only a wafer area corresponding to the exposure field of the photomask is partially secured. At this time, in order to prevent the generation of exposure failure during pattern transfer, a barrier (fence) for suppressing pattern transfer is placed in the edge region of the wafer corresponding to a part of the field area, so as to prevent pattern transfer during exposure. fail. This barrier can be formed by a separate first photoresist layer coating and first exposure process. A second layer of photoresist is applied to cover the fence. The pattern for realizing the wafer pattern on the wafer is exposed by a second exposure on the second photoresist layer.

[0036] In order ...

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Abstract

A method for forming patterns on a wafer includes forming a fence having a sloped face in an edge portion of the wafer. The sloped face is direct to an inside of the wafer. A first photoresist layer is formed which extends to cover the fence on the wafer. First photoresist patterns are formed by performing a first exposure and development on the first photoresist layer. An etch process is performed using the first photoresist patterns and the fence as an etch mask. The fence is formed by selectively exposing a negative resist using a light shielding blade, and at this time, the first photoresist layer is formed including a positive resist.

Description

[0001] Cross References to Related Applications [0002] Priority is claimed from Korean Patent Application No. 10-2009-0038126 filed on Apr. 30, 2009, the entire disclosure of which is incorporated by reference. technical field [0003] The present invention relates generally to a semiconductor device, and more particularly, to a method of fabricating a pattern on a wafer through an exposure process. Background technique [0004] A photolithography process is performed to integrate semiconductor devices on the wafer. The photoresist pattern is formed by transferring the layout of the circuit pattern formed on the photomask to the photoresist layer on the wafer by an exposure process, and by including an etching process (using the photoresist A patterning process using a resist pattern as an etching mask) to form a wafer pattern according to the layout of the designed circuit pattern. [0005] figure 1 A photomask used in a photolithography process is shown. refer to fi...

Claims

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Application Information

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Patent Type & AuthorityApplications(China)
IPC IPC(8): H01L21/027H01L21/8242H10B12/00
CPCH01L27/10852H01L21/31144H01L27/0207G03F7/0035H01L27/10894H01L21/0274H01L28/91G03F7/2022H10B12/033H10B12/09H01L21/32139
Inventor梁铉祚
OwnerSK HYNIX INC