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Method for realizing MPSoC (Multi-Processor System on Chip)-oriented transaction memory

A transactional memory and implementation method technology, applied in the field of transactional memory implementation, can solve the problems of no SPM utilization, high energy consumption, low efficiency, etc., and achieve the effects of speeding up processing speed, low energy consumption, and low energy consumption

Inactive Publication Date: 2011-09-21
WUHAN UNIV OF SCI & TECH
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Problems solved by technology

[0008] In the existing transactional memory implementation methods, SPM is not effectively utilized; and the existing various transactional memory implementation methods themselves also have problems such as low efficiency or high energy consumption

Method used

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  • Method for realizing MPSoC (Multi-Processor System on Chip)-oriented transaction memory
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  • Method for realizing MPSoC (Multi-Processor System on Chip)-oriented transaction memory

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Embodiment Construction

[0048] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, which are not intended to limit the protection scope thereof.

[0049] An implementation method of MPSoC-oriented transactional memory. The steps of this implementation method are as follows figure 1 Shown:

[0050] The first step, SPM space division

[0051] For the SPM space with a size of M, first divide the nested transaction stack space with a size of P for the nested transaction; for the memory operation in each transaction object, the space occupied in the SPM space is s, and the division is completed The number n of memory operations that can be stored in the SPM space is:

[0052] n=(M-P) / s (1)

[0053] The storage format of each memory operation in the SPM space consists of the memory operation owner, conflict flag, address, modified data, and original data.

[0054] In transactional memory, its operation on memory is called transa...

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Abstract

The invention relates to a method for realizing an MPSoC (Multi-Processor System on Chip)-oriented transaction memory. According to the technical scheme, the method comprises the following steps of: 1, partitioning an SPM (Scratch Pad Memory) space and partitioning a nested transaction stack space of which the size is P for a nested transaction specific to an SPM space of which the size is M, wherein if the space occupied by memory operation in each transaction object in the SPM space is s, the quantity n of memory operations which can be stored in the partitioned SPM space is equal to (M-P) / s; 2, executing an MPSoC-oriented transaction object; 3, nesting the MPSoC-oriented transaction object; 4, rolling the MPSoC-oriented transaction object back; and 5, defining an interface of MPSoC-oriented transaction memory operation. The method is suitable for an MPSoC-oriented transaction memory; and by adopting the method, the characteristics of high access speed and low energy consumption of the SPM are fully utilized, the transaction processing speed is increased, power consumption on transaction processing is reduced, and the performance of the transaction memory is enhanced.

Description

technical field [0001] The invention belongs to the technical field of embedded system transaction memory, in particular to an implementation method of MPSoC-oriented transaction memory. Background technique [0002] With the continuous progress of semiconductor technology, the integration density of VLSI (Very Large-Scale Integrated) is increasing significantly. The continuous improvement of integration on a single chip has enabled the development and application of SoC technology. SoC technology integrates all functional modules of a system into a single chip, so as to realize the integration of complete system functions on a single chip. [0003] MPSoC (MultiProcessor System on Chip) is a further development of SoC technology, which refers to a SoC with more than one embedded instruction set processor. MPSoC combines the characteristics of SoC technology and multi-core technology. Multi-core technology refers to the integration of multi-core processor cores on a chip t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/02
CPCY02B60/1225Y02D10/00
Inventor 胡威陈建勋卢建华邵平凡郭宏张凯刘小明张鸿陈姚节
Owner WUHAN UNIV OF SCI & TECH
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