Clock converting and locking method and circuit

Abstract

The invention discloses a clock converting and locking method, comprising the steps of: providing a clock A with square wave and a clock B with sine wave; computing a frequency common divisor of the frequency values of the two clocks to serve as a common division frequency for the conversion of the two clocks; obtaining the common division reference clock frequency of the clock A by using a counting frequency-dividing way; performing A / D (Analog to Digital) sampling to the clock B to obtain the sampling frequency of the clock B by using the common division reference clock frequency as a parameter; using the common division reference clock frequency and the sampling frequency as the parameters to design a phase-locked loop; accessing the output frequency of the phase-locked loop into the frequency control end of the clock B, thereby completing the closed-loop work of the whole system; the lock and the conversion of the clock A to the clock B are implemented under the circumstance of requiring no frequency multiplication to a high multiple frequency.

Description

Technical field [0001] The present invention relates to the field of communication and navigation, in particular to a clock conversion and locking method and its circuit. Background technique [0002] In communication and navigation systems, in order to achieve frequency conversion and locking, reference clocks, radio frequency clocks or other used clocks are commonly used, and the frequency conversion method of frequency multiplication or frequency division is used to obtain various frequencies required by the equipment. Appropriate lock times components to achieve. [0003] The phase-locked loop technology can achieve frequency multiplication and output a stable multiplication clock, and the phase relationship between the output clock and the input clock is constant, and in some designs, this phase relationship can also be adjusted according to system needs. But the disadvantage of this method is that the phase-locked loop has a certain bandwidth and requires the frequency range...

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a clock conversion and locking method and its circuit, which solves the frequency limitation of the frequency division and multiplication circuit in the traditional clock conversion and locking design and the relatively complicated problems of the circuit, especially for two clocks The complex relationship of locking multiples may lead to the problem that the frequency is difficult to lock

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