Multi-core processor and multi-core processor set

A multi-core processor and internal memory technology, applied in electrical digital data processing, instruments, multi-programming devices, etc., can solve the problems of increasing on-chip bus conflicts, the number of expansion cores cannot be too many, the overall structure is complex, etc., to improve communication. Efficiency, great application flexibility, the effect of reducing communication conflicts

CN102446158BActive Publication Date: 2013-09-18JIANGNAN INST OF COMPUTING TECH
1 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Publication Date
2013-09-18

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention relates to a multi-core processor and a multi-core processor set. The multi-core processor comprises at least one master core, at least one slave array, a first interconnecting structure and a slave core interconnecting structure, wherein the slave core array comprises a plurality of slave cores which are heterogeneous with the master core; the first interconnecting structure and the slave core interconnecting structure are used for communication between the master core and the slave core array; the slave core interconnecting structure is used for communication between any two slave cores in the slave core array; and as an optimized technical scheme, the master core is a universal processor core, the slave cores are processor cores microstructures and instruction sets of which are simplified and optimized, and the multi-core processor is integrated on the same chip. According to the multi-core processor and the multi-core processor set disclosed by the invention, communication efficiency among the processor cores is improved, calculation density of the whole multi-core processor is increased and balance between universal control function and high calculation density is realized.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The present invention relates to the field of processors, in particular to a multi-core processor and a multi-core processor group. Background technique

[0002] With the development of information technology, the demand for the processing power of computer processors is getting higher and higher, and traditional single-core processors can no longer meet the needs. Therefore, multi-core processors and many-core processors -core processor) has gradually been widely used. Multi-core processor refers to the integration of two or more processor cores in one processor. By dividing tasks among the cores, the parallel operation of multiple processor cores is realized, thereby improving the operation of the entire processor. processing power.

[0003] Multi-core processors can be divided into homogeneous multi-core processors and heterogeneous multi-core processors. Homogeneous multi-core processors include multiple processor cores with the same structure, w...

Examples

Embodiment Construction

[0050] In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0051] In the heterogeneous multi-core processors of the prior art, all processor cores are generally connected to the same bus, which increases the number of conflicts in the communication process and lowers the communication efficiency, and in order to avoid excessive conflicts, the number of slave cores is often small. , which affects the improvement of the computing density of the entire heterogeneous multi-core processor.

[0052] The technical solution of the present invention adopts a two-level interconnection structure, wherein the first interconnection structure is used for the communication between the master core and the slave core array, and the slave core interconnection structure is used for any two slave...