Stacking type semiconductor packaging structure and manufacturing method thereof

Abstract

The invention discloses a stacking type semiconductor packaging structure and a manufacturing method thereof. The structure comprises a first packaging body and a second packaging body. The first packaging body comprises a first carrier, a first chip, a first conductive member and a first plastic packaging body, wherein the first chip is arranged on the first carrier and is electrically connected to the first carrier; the first chip comprises a first surface facing the first carrier and a second surface which is opposite to the first surface; the first conductive member comprises a first end and a second end; the first end is arranged on the second surface of the first chip and is electrically connected to the second surface of the first chip; the first plastic packaging body covers the first carrier, the first chip and the first end of the first conductive member, and exposes the second end of the first conductive member. The second packaging body comprises a second carrier, a second chip, a second conductive member and a second plastic packaging body, wherein the second chip is arranged on the second carrier and is electrically connected to the second carrier; the second conductive member protrudes out of the second carrier and is electrically connected to the second chip; and the second plastic packaging body covers the second carrier and the second chip. The second conductive member is inserted into the second end of the first conductive member.

Description

technical field [0001] The present invention relates to the field of semiconductor packaging, more specifically, to a stacked semiconductor packaging structure and a manufacturing method thereof. Background technique [0002] As electronic devices become smaller in size, high integration density is achieved by stacking a plurality of chips or stacking semiconductor packages in one semiconductor package structure. A stacked semiconductor package structure is a stacked package structure in which a logic package and a memory package are embedded in one package. With the stacked semiconductor packaging technology, different types of semiconductor devices can be included in one semiconductor packaging structure. [0003] Figure 1A and Figure 1B It is a structural sectional view and a stacking schematic diagram of a repeatable stackable package disclosed in CN101221945A. refer to Figure 1A , the repeatable stackable package 100 includes: a substrate 110 having a first surfac...

AI Technical Summary

Problems solved by technology

[0006] in reference to figure 2 In the described stacked semiconductor package structure, a part of the connection pattern 212 and the solder ball 208a used for the stacking and electrical connection of the two packages are exposed to the air, and are easily degraded by moisture in the air, resulting in an unreliable electrical connection.

Images