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Storing secure mode page table data in secure and non-secure regions of memory

A security mode and security area technology, applied in the field of data processing systems, can solve the problems of large size of security mode page table data, unauthorized modification of security mode page table data, disadvantages, etc.

Active Publication Date: 2012-11-28
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A problem that may arise is that the secure mode page table data used to manage access to secure areas of memory may be subject to unauthorized modification, e.g. an application in secure mode will access a non-secure area of ​​memory instead of the original access to secure areas of memory as intended
However, one problem with this approach is that the size of the secure mode page table data is large and disadvantageously consumes a large amount of memory capacity of one or more secure regions of memory
Therefore, although the amount of secure data itself such as encryption keys, financial data, secure program instruction codes is relatively small, just to store secure mode page table data, it may be necessary to have a large storage capacity in the secure area of ​​the memory

Method used

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  • Storing secure mode page table data in secure and non-secure regions of memory
  • Storing secure mode page table data in secure and non-secure regions of memory
  • Storing secure mode page table data in secure and non-secure regions of memory

Examples

Experimental program
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Embodiment Construction

[0054] figure 1 A data processing system 2 is schematically shown comprising a system-on-chip integrated circuit 4 and a separate non-secure memory integrated circuit 6 . The system-on-chip integrated circuit 4 includes processing circuitry in the form of a processor 8, which controls an instruction decoder 12 in response to program instructions I received in an instruction pipeline 10 to generate control signals to configure and control components including register banks 14, multipliers, 16. The data path of the shifter 18 and the adder 20. Processor 8 performs data processing operations under the control of program instructions I. These data manipulation operations include memory access operations, which attempt to read data from or write data to memory addresses within the system's memory address space. Not all memory address spaces may be associated with actual physical memory capable of storing data values, eg, some address spaces may not be available for use. A certa...

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PUM

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Abstract

Apparatus for data processing (2) is provided with processing circuitry (8) which operates in one or more secure modes (40) and one or more non-secure modes (42). When operating in a non-secure mode, one or more regions of the memory are inaccessible. A memory management unit (24) is responsive to page table data to manage accesses to the memory which includes a secure memory (22) and a non-secure memory (6). Secure mode page table data (36, 38) is used when operating in one of the secure modes. A page table entry within the hierarchy of page tables of the secure mode page table data includes a table security field (68, 72) indicating whether or not a further page table pointed to by that page table entry is stored within the secure memory (22) or the non-secure memory (6).If any of the page tables associated with a memory access are stored within the non-secure memory (6), then the memory access is marked with a table attribute bit NST indicating that the memory access should be treated as non-secure.

Description

technical field [0001] The present invention relates to data processing systems. In particular, the present invention relates to a data processing system having one or more secure modes of operation and one or more non-secure modes of operation and utilizing secure mode page table data to manage access to memory while operating in the secure mode. Background technique [0002] It is known to provide a data processing system having one or more secure modes of operation and one or more non-secure modes of operation, such as the TrustZone architecture developed by ARM Limited, Cambridge, UK processing system. The memory (memory address space) in such a system is typically provided with one or more secure regions and one or more non-secure regions, which are accessible in the secure mode of operation and mode, and the one or more non-secure regions are accessible in both the secure mode of operation and the non-secure mode of operation. In this way, sensitive data such as enc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/10G06F12/14
CPCG06F12/145G06F12/1009G06F12/1027G06F2212/50
Inventor 理查德·罗伊·格里森思怀特
Owner ARM LTD
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