Design method for reducing crosstalk influence between high-speed differential pairs

A high-speed differential pair, design method technology, applied in computing, special data processing applications, instruments, etc., can solve problems affecting product quality stability, voltage generation, crosstalk, etc., to improve the quality of high-speed signal crosstalk, promote development costs, The effect of stable product quality

Active Publication Date: 2014-12-03
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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Problems solved by technology

Therefore, the improvement of signal speed and the increase of layout high-speed wiring density will make the influence of crosstalk effect between signals more significant, thus affecting the stability of product quality
[0003] Due to the parasitic inductance and capacitance effect on the signal propagation path when laying out the PCB main board, when the signal propagates on a PCB Trace path, it will inevitably propagate to other adjacent ones through the coupled parasitic inductance and capacitance. Trace, and generate voltage noise on the near end and far end of its Victim Trace, thereby introducing crosstalk

Method used

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  • Design method for reducing crosstalk influence between high-speed differential pairs
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  • Design method for reducing crosstalk influence between high-speed differential pairs

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[0022] Below with reference to accompanying drawing, by specific embodiment, the present invention is further described:

[0023] Such as Figure 4 As shown, a design method to reduce the influence of crosstalk between high-speed differential pairs, by changing the placement position of the DC coupling capacitor in the middle of the differential pair, the polarity of the traces of the differential pair is reversed before and after the DC coupling capacitor, that is, by polarity The opposite polarity is transformed into the same polarity, so that the positive and negative amplitude noise of the far-end crosstalk overlaps each other, weakening the differential total noise energy.

[0024] In the distribution of several pairs of differential lines, the differential lines with the same polarity before and after the DC coupling capacitor and the differential lines with opposite polarity before and after the DC coupling capacitor are arranged at intervals.

[0025] Such as Figure...

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Abstract

The invention discloses a design method for reducing crosstalk influence between high-speed differential pairs. Polarity of the parts, in front and rear of DC (direct current) coupling capacitors, of differential pair lines is reversed; crosstalk positive and negative amplitude noises of far ends are mutually stacked; differential overall noise is weakened. Theoretical analysis and simulation verification show that the design method has the effect of improving crosstalk quality of high-speed signals on high-density layout PCBs (printed circuit boards); by the use of the design method, development cost of products can be lowered, product quality is stable, and the products are more competitive in the market.

Description

technical field [0001] The invention relates to the field of PCB design, in particular to a design method for reducing the influence of crosstalk between high-speed differential pairs. Background technique [0002] At present, the PCB design of server products is tending to develop in the direction of high signal rate and high wiring density. Such a design method can improve product performance and reduce product production costs, thereby enhancing the competitiveness of products in the market. Then, it also increases the difficulty of design. For example, in order to reduce product cost, the number of stacked design layers can be reduced, which greatly increases the difficulty of high-speed wiring, and the reduction of space between differential pairs will increase the difference between differential pairs. Inter-coupling, resulting in an increase in crosstalk strength. At the same time, due to the increase of signal speed, it means that the signal rise time is shortened,...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 武宁吴福宽
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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