FPGA (Field Programmable Gate Array) interactive simulation method based on Tcl (Tool Command Language)

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) interactive simulation method based on Tcl (Tool Command Language). The method comprises the steps of 1) establishing a Tcl interpreter in an FPGA verification platform verilog, and establishing a communication channel between the verilog and the Tcl; 2) creating a test case in the verilog by the Tcl; 3) calling the test case by the Tcl interpreter; when the Tcl interpreter receives a write operation command name, the Tcl interpreter calls the write operation task in the verilog according to the write operation command and transmits the address and data for performing the write operation to the verilog to switch process; when the Tcl interpreter receives a read operation command name, the Tcl interpreter calls the read operation task in the verilog according to the read operation command and transmits the data for performing the read operation to the verilog to switch process; when the Tcl interpreter receives a wait operation command name, the Tcl interpreter calls the wait operation task in the verilog according to the wait operation command; 4) after finishing the task of the verilog, returning a return value to the Tcl interpreter and switching the process. By adopting the method, the workload of developing and debugging the test case is reduced; the simulation process can be controlled in real time.

Description

technical field [0001] The invention relates to a Tcl-based FPGA interactive simulation method, which belongs to the technical field of computer software. technical background [0002] With the increasing capacity and scale of FPGA, the complexity of FPGA design is getting higher and higher. In order to ensure the quality of design, FPGA verification engineers need to use Verilog or Systemverilog language to build a verification platform and write test cases and use simulation tools to test FPGA. Functional simulation. At the same time, the FPGA engineer needs to convert the FPGA code into a loading file and download it to the FPGA device for board-level testing. In board-level testing, FPGA engineers also need to write test scripts based on software drivers to perform board-level testing on FPGAs. FPGA simulation is to verify the design code of FPGA. The advantage of this method is that the simulated waveform can be seen directly, which is convenient for FPGA engineers to...

AI Technical Summary

Problems solved by technology

In addition, there is a certain amount of repetitive work to develop and test test cases for the same function on the simulation platform and the board-level test platform.

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