Semiconductor memory device and programming method thereof

Abstract

The invention provides a semiconductor memory device and a programming method thereof, which not only maintains reliability of data but also reduces programming time. A NAND-type flash memory loads programming data inputted from an external input / output terminal to a page buffer / sensing circuit. A detection circuit for monitoring the programming data detects whether the programming data is a special bit string, if the programming data is not the special bit string, a transmission / writing circuit transfers the programming data maintained in the page buffer / sensing circuit to an error detection correcting circuit and writes an error correcting code, which is generated through error detection correcting computation, to the page buffer / sensing circuit; and if the programming data is detected to be the special bit string, data transmission of the programming data maintained in the page buffer / sensing circuit is forbidden, and meanwhile, a known error correcting code being corresponding to the special bit string is written to the page buffer / sensing circuit.

Description

technical field [0001] The present invention relates to a semiconductor storage device and a programming method thereof, to error detection and correction of input and output data of the semiconductor storage device, and in particular to error detection and correction of input data of a NAND type flash memory (FlashMemory) . Background technique [0002] Semiconductor memories such as flash memory and dynamic random access memory (Dynamic Random Access Memory, DRAM) increase year by year due to the integration level, so it is difficult to manufacture storage elements without faults or defects. Therefore, on the memory chip, a redundancy scheme (redundancy scheme) for visually remedying physical defects of memory elements generated in the manufacturing steps is adopted. For example, in a certain redundancy scheme, a physically defective storage element is remedied by setting a redundant memory. Furthermore, in the semiconductor memory, in addition to the physical recovery o...

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Problems solved by technology

Furthermore, Patent Document 3 discloses a flash memory in which an ECC parity (Error Checking Correction parity) is added to input data to generate an ECC code, and the generated ECC code is written into a physical block, and the When there is an error in the page (page) data read from the physical block, use the ECC code to correct the error, and register the physical block with the number of corrected errors above the threshold as a warning block in the table, and select it when writing data. The priority of the warning block is lowered

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