A system-level hardening method for asic space applications
A system-level and space-based technology, applied in program loading/starting, program control design, instrumentation, etc., can solve problems such as increasing power consumption or area, wasting power consumption and chip area, and failing to solve the single event function interruption of ASIC device system , to achieve the effect of ensuring applicability and improving single event interruption ability
Active Publication Date: 2017-07-11
湖南省导航仪器工程研究中心有限公司
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According to current research, the influence of single event effects is different on different space orbits. If a single reinforcement measure is taken, it may not be possible to optimize the operation of the dedicated chip, wasting unnecessary power consumption and chip area
[0005] It can be seen from the above that the existing ASIC devices for space applications mainly use redundancy or physical design reinforcement measures from the chip design stage. This design is to increase the reliability of ASIC device space applications at the cost of increasing power consumption or area. This method cannot solve the system single event function interruption caused by the space radiation effect of ASIC devices
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[0044] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0045] Such as figure 1 As shown, a kind of system-level reinforcement method for ASIC space application of the present invention, its steps are:
[0046] S1: Establish a list of configuration parameters, and define the parameters that need to be configured according to the function definition and requirements of the chip;
[0047] S2: Reinforcement design of the parameter configuration list, and reliability reinforcement design for the defined parameters to be configured;
[0048]S3: Design a real-time verification and timing refresh mechanism, that is, after the chip works normally, the chip repeatedly verifies the configuration parameters; according to different space application environments, that is, the satellite orbit parameters and the register flip probability of this orbit condition, set Set the interval time for regular r...
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The invention discloses a system-level reinforcement method for an ASIC spatial application. The method comprises the steps of: S1: establishing a parameter configuration list; S2: performing reinforcement setting on the parameter configuration list, and performing reliability reinforcement on defined to-be-configured parameters; S3: setting a real-time checking and periodic refreshing mechanism; S4: setting a chip system-level dynamic refreshing mechanism, and performing register cache mode setting on parameters required to be configured; S5: setting a chip parameter re-configuration protection mechanism to ensure the correctness of a re-configuration process; S6: storing reinforced chip configuration parameters; S7: reading external configuration parameters to finish initial configuration; S8: after the initial configuration is finished, starting to perform real-time checking on configuration parameters working in a chip; S9: re-configuring the time according to the set parameters; and S10: performing dynamic refreshing. The method has the advantages of easiness for realization, high reliability, wide application range and the like.
Description
technical field [0001] The present invention mainly relates to the technical field of electronic system-level reliability hardening, in particular to a system-level hardening method for ASIC space applications Background technique [0002] The integrated circuit chip in the electronic system operates in the space radiation environment, and is affected by the radiation of space high-energy particles, which is very easy to produce single event effects. The single event effect will cause damage to the integrated circuit itself or abnormal function operation, which will lead to abnormal function of the entire electronic system, and in severe cases will completely disable the function of the electronic system. As large-scale integrated circuits are used more and more in space electronic systems, the single event effect can cause the logic state of the integrated circuit to flip, the transient abnormality or interruption of the logic function, and with the CMOS (Complementary Meta...
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IPC IPC(8): G06F9/445
CPCG06F9/4451
Inventor 王跃科杨俊杨建伟杨光邢克飞何伟
Owner 湖南省导航仪器工程研究中心有限公司