Parallel computing network division method capable of absorbing interface delays of different step lengths

A parallel computing and interface technology, applied in computing, special data processing applications, instruments, etc., can solve problems that affect simulation stability, have no versatility, and have no stability.

Active Publication Date: 2016-05-25
CHINA ELECTRIC POWER RES INST +3
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This method is less parallel and less accurate when dealing with perturbations
[0007] None of the above meth

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  • Parallel computing network division method capable of absorbing interface delays of different step lengths
  • Parallel computing network division method capable of absorbing interface delays of different step lengths
  • Parallel computing network division method capable of absorbing interface delays of different step lengths

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Embodiment Construction

[0049] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0050] The following description and drawings illustrate specific embodiments of the invention sufficiently to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely represent possible variations. Individual components and functions are optional unless explicitly required, and the order of operations may vary. Portions and features of some embodiments may be included in or substituted for those of other embodiments. The scope of embodiments of the present invention includes the full scope of the claims, and all available equivalents of the claims. These embodiments of the present invention may be referred to herein, individually or collectively, by the term "invention", which is for convenience only and is not...

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Abstract

The invention relates to a parallel computing network division method capable of absorbing interface delays of different step lengths. The method comprises the following steps: step 1: determining a transmission line port equation of a Thevenin equivalent circuit incorporating into a sub-network; step 2: performing different step length simulation of transmission line decoupling; step 3: performing preset simulation step length discretization on a sub-network I and a sub-network II; and step 4: simulating the discretized simulation step length. The method can realize complete parallel simulation and is an ideal simulation method in real-time simulation. A transmission line suitable for network division in a network needs to be found by applying a different step length simulation algorithm based on the transmission line and is transformed into a transmission line model of a big step length delay, and the network is decoupled through the model. A computing error caused by no interface delays during electromagnetic transient parallel network division of different step lengths can be realized and numerical oscillations and simulation errors caused by the interface delays can be reduced or avoided.

Description

technical field [0001] The invention relates to a simulation method for electromagnetic transient simulation, in particular to a parallel calculation network division method for absorbing interface delays of different step lengths. Background technique [0002] The degree of parallelization of different step-length simulation technology algorithms is not high, and the amount of system interaction information is large, so it is difficult to realize real-time simulation. The parallel interface algorithm can decouple the networks on both sides, improve the parallelism of simulations with different step lengths, and reduce system interaction information, which is a possible solution for real-time simulation. [0003] After investigation, the currently available parallel simulation interfaces with different step lengths include the following methods: [0004] The ITM method is a direct method, which divides the circuit according to the tie line, and one side is represented by a ...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/367
Inventor 郑伟杰穆清周飞陆振纲于鸿洋张磊徐树文彭红英张星王祥旭张艳
Owner CHINA ELECTRIC POWER RES INST
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