Memories with sub-block erase architecture

Abstract

The invention provides a memory device, which has a divided reference lines structure. The structure supports sub-block erase of an NAND memory containing multiple blocks. Each block in the multiple blocks is coupled to a group of Y reference lines, wherein Y is equal to or greater than 2. Each block in the multiple blocks contains a single reference select line (RSL) capable of operating to connect each sub-block in the block to a corresponding reference line in the group of Y reference lines. A control circuit can be included in the device, and can be configured to carry out erase operation so as to erase a selected sub-block in a selected block.

Description

technical field [0001] The present invention relates to high density memory devices, and in particular to memory devices comprising three-dimensional arrays. Background technique [0002] As the critical dimensions of devices in integrated circuits shrink to the limits of typical memory cell technology, designers have paid attention to techniques for stacking multiple planes of memory cells to achieve larger memory capacities and lower cost per bit. For example, the thin-film transistor technology of Lai et al. has been applied to the charge trapping memory technology. Jung et al. presented "A Multi-Layer Stackable Thin-Film Transistor (TFT )NAND-Type Flash Memory", "ThreeDimensionally Stacked NAND Flash Memory Technology Using Stacking SingleCrystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node" at the IEEE International Electron Devices Conference on December 11-13, 2006. [0003] An alternative structure providing vertical NAND string-to-charge-trapping memor...

AI Technical Summary

Problems solved by technology

Also, memory management routines (routines) operating on block boundaries require erase and program operations to move data around, and program and erase cycles consume the cycle tolerance of memory cells

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