Sensing circuit for nonvolatile memory device and nonvolatile memory device

A sensing circuit and voltage technology, applied in information storage, static memory, read-only memory, etc., can solve problems such as jump point difference and influence on the accuracy of electrical characteristics, and achieve the effect of accurate data value and accurate sensing

Active Publication Date: 2019-10-11
POWERCHIP SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Also, if the P-channel MOS transistors and N-channel MOS transistors are arranged with a slight deviation, the deviation of the trip point may differ by more than 10% in the worst case.
In this way, variations in the electrical characteristics of MOS transistors will have a large impact on the accuracy of sensing in further miniaturized flash memories.

Method used

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  • Sensing circuit for nonvolatile memory device and nonvolatile memory device
  • Sensing circuit for nonvolatile memory device and nonvolatile memory device
  • Sensing circuit for nonvolatile memory device and nonvolatile memory device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0175] Figure 7 It is a circuit diagram showing a configuration example of the sensing circuit 30A and the page buffer PBn for the NAND flash EEPROM of the first embodiment. Figure 7 In the first embodiment, the sensing circuit 30A is provided for each of the page buffers PBn, and is provided between the nodes SNS and SLS1 of the page buffer PBn and the signal line B, and has a stacked gate type An N-channel MOS transistor N1 and two N-channel MOS transistors N2 and N3 as switching elements are formed.

[0176] The control gate of the MOS transistor N1 is connected to the node SNS (the sensing node of the page buffer PBn), the floating gate of the MOS transistor N1 is connected to the source of the MOS transistor N2, and the source of the MOS transistor N1 is connected to the signal line B. The drain of the MOS transistor N1 is connected to the source of the MOS transistor N3 and the drain of the MOS transistor N2. Furthermore, to the gate of the MOS transistor N2, a sensing de...

Embodiment 2

[0192] Picture 9 It is a circuit diagram showing a configuration example of the sensing circuit 30B and the page buffer PBn for the NAND flash EEPROM of the second embodiment. In addition to data reading, the sensing circuit 30B of the second embodiment is also used for data programming and verification processing (including the case where the node voltage SLR1 is low and programming is performed, and the node voltage SLR1 is high without performing Programming case) the sensing circuit, and Figure 7 Compared with the sensing circuit 30A of the first embodiment, the following aspects are different.

[0193] (1) In addition to the MOS transistors N1 and N2, the sensing circuit 30B is composed of an N-channel MOS transistor N5 and an N-channel MOS transistor N4. The N-channel MOS transistor N5 is a switch connected to the signal line A and the node SLS1 Component, the N-channel MOS transistor N4 is a switch component that is turned on / off based on the verification and judgment sw...

Embodiment 2-1

[0198] Picture 10 Is represented by Picture 9 A flowchart of the data programming and verification processing of the embodiment 2-1 executed by the sensing circuit 30B and the page buffer PBn (when SLR1 = Low and programming is performed and SLR1 = 0V, SLS1 = VDD) . Picture 10 Data programming and verification processing and Figure 8 Compared with the data read-out processing, the following aspects are different. In addition, in Picture 10 In each treatment, use the bottom line to indicate the Figure 8 The difference between the corresponding processing, the following also uses the underline to indicate the difference with the previous corresponding processing.

[0199] (1) Replace Figure 8 Steps S1 to S4 of, including the processing of steps S21 and S22.

[0200] (2) Replace Figure 8 Steps S8 and S12 include the processing of steps S8A and S12A, respectively.

[0201] (3) After the processing of step S13, execute Picture 11 The programming ends judgment processing (S14).

...

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Abstract

The present invention relates to a sensing circuit for a non-volatile memory device and a non-volatile memory device. The sensing circuit is provided in a page buffer including a latch that temporarily holds data when data is written to or read from a memory cell of the non-volatile memory device, and senses data. , the sensing circuit includes: a first switch component and a stacked gate type control component, which are connected in series between the first signal line and the first terminal of the latch; and a second switch component, which is connected between the first switch component and the stacked gate control component. Between the gate control components, before the sensing of turning on the first switch component by sensing the enable signal is started, the voltage of the floating gate of the stacked gate control component is set to be the same as that of the stacked gate control component. The threshold voltage seen by the floating gate is added to the specified voltage, and then the memory cell data is sensed.

Description

Technical field [0001] The present invention relates to a sensing device (Electrically Erasable Programmable Read-Only Memory (EEPROM)) for electrically rewritable non-volatile semiconductor storage devices such as flash memory. Circuits and non-volatile storage devices. Background technique [0002] There is known a NAND type nonvolatile semiconductor memory device in which a plurality of memory cell transistors (hereinafter referred to as NAND) are connected in series between a bit line and a source line. It is called a memory cell to form a NAND string, thereby achieving high integration (for example, refer to Patent Document 1). [0003] Figure 1A It is a block diagram showing the overall structure of a conventional NAND flash EEPROM. and, Figure 1B Yes means Figure 1A A circuit diagram of the configuration of the memory cell array 10 and its peripheral circuits. [0004] in Figure 1A Among them, the NAND flash EEPROM of the conventional example is provided with a memory cell...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): G11C16/26G11C16/10
CPCG11C16/10G11C16/26
Inventor小川晓
OwnerPOWERCHIP SEMICON MFG CORP