A method to reduce finfet parasitic resistance

Abstract

A device structure for reducing FinFET parasitic resistance and its preparation method, the method comprising: preparing a conventional FinFET device structure, including preparing a FinFET silicon fin structure, a gate stack structure composed of a gate electrode and a gate dielectric layer, and defining the source and drain of the FinFET device The sub-steps of the region; wherein, the conventional FinFET device structure includes a gate stack structure composed of a metal gate electrode and a gate dielectric layer to wrap the FinFET silicon fin structure from the side and surface, respectively, to form a three-dimensional channel of the MOSFET; prepare a catalyst layer in the source and drain regions ; Grow carbon nanotubes to form a strip-shaped contact hole layer M0; wherein, the lower end of the strip-shaped contact hole layer M0 covers and connects the source and drain regions of the FinFET device; carbon nanotubes include single-wall and multi-wall carbon nanotube materials; realize FinFET The source and drain extraction of the device and subsequent process preparation, even if the upper end of the strip-shaped contact hole layer M0 is connected to the metal layer M1.

Description

technical field [0001] The invention relates to a manufacturing process of semiconductor products in the field of integrated circuit manufacturing, in particular to a method for reducing parasitic resistance of a fin field-effect transistor (Fin Field-Effect Transistor, FinFET for short). Background technique [0002] As semiconductor process technology nodes continue to shrink, traditional planar metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET for short) encounter more and more technical challenges. [0003] As a new type of three-dimensional device structure, FinFET can greatly improve the device characteristics of MOSFET. These device characteristics can include suppressing short channel effect (SCE), reducing device leakage, increasing drive current, and improving sub-threshold characteristics. [0004] At present, the world's leading semiconductor foundries have mass-produced FinFET technology in the 16 / 14nm ...

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