Flash memory and manufacturing method thereof
A manufacturing method and flash memory technology, applied in the manufacture of flash memory and the field of flash memory, can solve the problems of reducing the distance of flash memory cells and affecting the performance of flash memory cells, and achieve the effect of simple process
Patent Information
- Authority / Receiving Office
- CN · China
- Current Assignee / Owner
- Publication Date
- 2018-07-27
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Abstract
Description
technical field
[0001] The invention relates to the field of semiconductor integrated circuits, in particular to a flash memory (Flash), and also to a method for manufacturing the flash memory. Background technique
[0002] Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, and electrical programmability and erasability. At present, flash memory cells are mainly implemented at the 65nm technology node. With the demand for large-capacity flash memory, the number of chips on each silicon wafer will be reduced by using the existing technology nodes. At the same time, the increasing maturity of new technology nodes also urges flash memory cells to be produced with high-node technology, which means that the size of flash memory cells needs to be reduced.
[0003] The first type of flash memory unit is available:
[0004] Now the first common structure of flash memory cells has a contact hol...
Examples
Embodiment Construction
[0069] Please also refer to the layout structure of the flash memory of the embodiment of the present invention Figure 4 as shown, Figure 8 is the edge of the flash memory of the embodiment of the present invention Figure 4 Sectional view of CC line; Figure 9 is the edge of the flash memory of the embodiment of the present invention Figure 4 Sectional view of line DD in middle; Figure 4 It can be known from the layout structure that the storage area of the flash memory in the embodiment of the present invention includes a flash memory cell array formed by arranging a plurality of flash memory cells. Each flash memory cell of the flash memory cell array is formed in the same active area 201 . The top of the polysilicon row 202 formed by the polysilicon control gate 407 is connected to the word line formed by the front metal layer; the polysilicon floating gate 403 is connected to the Figure 4 The formation area in is shown in the dotted line box 203, the N+ diffus...