Data transmission apparatus for memory and data transmission method thereof

Abstract

The invention provides a data transmission apparatus for memory and a data transmission method thereof. The data transmission apparatus includes a prior stage shift register circuit and a plurality ofrear stage shift register circuits. The prior stage shift register circuit is coupled to a sense amplifying device of the memory, receives sensed data from the sense amplifying device and outputs a plurality of the readout data in series by bitwise shifting out the sensed data according to a shift clock signal. The plurality of rear stage shift register circuits are coupled to the prior stage shift register circuit and respectively coupled to a plurality of pads. The plurality of rear stage shift register circuits respectively receive the readout data and respectively bitwise transport the readout data to the pads according to a clock signal. Wherein, a frequency of the shift clock signal is less than a frequency of the clock signal.

Description

technical field [0001] The invention relates to a data transmission device and a data transmission method thereof, in particular to a data transmission device with a two-stage structure and a data transmission method thereof. Background technique [0002] Please refer to figure 1 , which shows a circuit diagram of an existing memory data transmission device. In the prior art, the main array 110 is coupled to the page buffer 120 and provides data for a read operation to the sense amplifier 130 through the page buffer 120 . The sense amplifier 130 senses the aforementioned data and provides the sensed data to the shift register 140 . The shift register 140 receives and latches the sensing data, and shifts out the sensing data bit by bit according to the clock signal CLK, and directly provides the shifted data to a plurality of pads PD1 to PD4 . [0003] The budget for data propagation from shift register 140 to pads PD1 to PD4 is half the clock period (1 / 2 CLK). Data propa...

AI Technical Summary

Problems solved by technology

Data propagation may limit the speed of the design, especially in the case of large chip sizes, data propagation from shift register 140 to pads PD1 to PD4 may become a bottleneck for maximum speed

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