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Dynamic binary translation method and device for vliw architecture

A dynamic binary and translation device technology, applied in the computer field, can solve the problems of low performance of VLIW programs, and achieve the effects of reducing overhead, ensuring correctness, and improving execution performance.

Active Publication Date: 2022-02-08
康烁
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  • Abstract
  • Description
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Problems solved by technology

[0006] The main purpose of the present invention is to provide a kind of dynamic binary translation method and device oriented to VLIW framework, to solve the problem that the target processor in the prior art executes the low performance of VLIW program

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  • Dynamic binary translation method and device for vliw architecture
  • Dynamic binary translation method and device for vliw architecture
  • Dynamic binary translation method and device for vliw architecture

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Embodiment Construction

[0026] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. It should be pointed out that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0027] VLIW (Very Long Instruction Word, Very Long Instruction Word) is a microprocessor architecture that allows multiple instructions to be arranged in a very long (128--1024 bits) very long instruction word and enters the pipeline for execution. A single operation of a VLIW architecture microprocessor has a definite execution cycle, and the correctness of the program is realized by the compiler scheduling.

[0028] figure 1 It is the process flow of the dynamic binary translation method according to an optional embodiment of the present invention Figure 1 ,Such asfigure 1 As shown, the method includes the following steps:

[0029] Step S1: Obtain a basic block, which co...

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Abstract

The invention discloses a dynamic binary translation method and device for VLIW architecture. The method includes obtaining a basic block; checking whether there is a delay operation after executing the previous basic block in the execution delay slot queue; if it exists, enter the original mode to translate the basic block; if not, enter the fast mode to translate the basic block, and check the translation Whether there are delayed operations delayed to this cycle in the delay slot queue; if so, directly translate the delayed operations delayed to this cycle into the local code of the corresponding operation, and remove the delayed operations delayed to this cycle from the queue; translation Periodic instruction, if there is a delay operation in this cycle instruction, the delay operation will be written into the translation delay slot queue; after the translation of the basic block, if there are still delay operations left, the delay operation will be moved to the execution delay slot queue; schema and original schema translated native code. Through the present invention, the performance of executing translation programs can be improved.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a dynamic binary translation method and device for VLIW architecture. Background technique [0002] Dynamic binary translation refers to the method of translating a binary program of a source processor into machine language on another target processor at runtime, so that the translated program can be executed on the target processor. In the binary translation method, the instruction flow of the source processor to be executed ends with a jump instruction to construct a single-input-single-out basic block, and the basic block is translated into native code on the target processor for execution. [0003] VLIW (Very Long Instruction Word, Very Long Instruction Word) is a microprocessor architecture that allows multiple instructions to be arranged in a very long (128--1024 bits) very long instruction word and enters the pipeline for execution. A single operation of a VLIW ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F8/52G06F12/1027
Inventor 康烁
Owner 康烁
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