36 results about "Delay slot" patented technology

By encoding an exception triggering value in storage referenced by an instruction in an otherwise unused slot (e.g., the delay slot of a delayed control transfer instruction or an unused instruction position in a VLIW-based architecture) coinciding with a safe point, an efficient coordination mechanism can be provided for multi-threaded code. Because the mechanism(s) impose negligible overhead when not employed and can be engaged in response to an event (e.g., a start garbage collection event), safe points can be defined at call, return and / or backward branch points throughout mutator code to reduce the latency between the event and suspension of all threads. Though particularly advantageous for thread suspension to perform garbage collection at safe points, the techniques described herein are more generally applicable to program suspension at coordination points coinciding with calls, returns, branches or calls, returns and branches therein.

A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. If the branch is mispredicted, the first tag is broadcast to pipeline stages that may have speculative instructions, and the first tag is compared to tags in the pipeline stages to determine which instructions to cancel. The assignment of tags for a fetch group of concurrently fetched instructions may be performed in parallel. A plurality of branch sequence numbers may be generated, and one of the plurality may be selected for each instruction responsive to the cumulative number of branch instructions preceding that instruction within the fetch group. The selection may be further responsive to whether or not the instruction is in a conditional delay slot.

A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. The second tag may equal the first tag if the branch delay slot is unconditional for that branch, and may equal a different tag if the branch delay slot is conditional for the branch. If the branch is mispredicted, the first tag is broadcast to pipeline stages that may have speculative instructions, and the first tag is compared to tags in the pipeline stages. If the tag in a pipeline stage matches the first tag, the instruction is not cancelled. If the tag mismatches, the instruction is cancelled.

The invention discloses a dynamic binary translation method and device for VLIW architecture. The method includes obtaining a basic block; checking whether there is a delay operation after executing the previous basic block in the execution delay slot queue; if it exists, enter the original mode to translate the basic block; if not, enter the fast mode to translate the basic block, and check the translation Whether there are delayed operations delayed to this cycle in the delay slot queue; if so, directly translate the delayed operations delayed to this cycle into the local code of the corresponding operation, and remove the delayed operations delayed to this cycle from the queue; translation Periodic instruction, if there is a delay operation in this cycle instruction, the delay operation will be written into the translation delay slot queue; after the translation of the basic block, if there are still delay operations left, the delay operation will be moved to the execution delay slot queue; schema and original schema translated native code. Through the present invention, the performance of executing translation programs can be improved.

A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. If the branch is mispredicted, the first tag is broadcast to pipeline stages that may have speculative instructions, and the first tag is compared to tags in the pipeline stages to determine which instructions to cancel. The assignment of tags for a fetch group of concurrently fetched instructions may be performed in parallel. A plurality of branch sequence numbers may be generated, and one of the plurality may be selected for each instruction responsive to the cumulative number of branch instructions preceding that instruction within the fetch group. The selection may be further responsive to whether or not the instruction is in a conditional delay slot.

The invention discloses a system and a method for processing a jump instruction of a microprocessor in a branch prediction way. The system comprises a coding module and a transmission module, wherein the coding module comprises a branch predictor used for predicting by adopting a static prediction method when the jump instruction to be processed is in the jump execution type or adopting a dynamic prediction method when the jump instruction to be processed is not in the jump execution type after the coding module judges that an instruction to be processed is the jump instruction and judges the type of the jump instruction through precoding, and directly writing the jump instruction to be processed and a delay slot instruction thereof in an operational queue in a sequence of the instructions in a program; and the transmission module comprises a prediction result processor used for canceling the instruction executed by error and continue fetching in a correct jump direction when the branch predictor predicts the jump instruction by error after the jump instruction is executed and written back to the transmission module. The system cancels operation by adopting different cancellation methods on the basis that whether the instruction is the jump execution instruction or not when the instruction is cancelled.

A processor is configured to identify a branch instruction immediately followed by an architectural delay slot. A single bonded instruction comprising the branch instruction immediately followed by the architectural delay slot is created. The single bonded instruction is loaded into an instruction buffer.

The invention discloses a processing method for calling a subprogram of a microprocessor, and a device for the same. The method comprises the following steps of: obtaining a subprogram calling instruction which carries an unsigned immediate; extracting the unsigned immediate from the subprogram calling instruction; obtaining the total number of the instructions in a delay slot according to the unsigned immediate; and obtaining the return address of the subprogram calling instruction according to the total number of the instructions in the delay slot. The device comprises the following units: an obtaining unit for obtaining the subprogram calling instruction, an extraction unit for extracting the unsigned immediate from the subprogram calling instruction, and a calculation unit for obtaining the total number of the instructions in the delay slot according to the unsigned immediate and calculating the return address of the subprogram calling instruction according to the total number of the instructions in the delay slot. According to the method and the device for the same, performance of the processor in the aspect of processing the subprogram calling instruction is greatly improved.

A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating 'makefiles' for purposes of simulation and / or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

The invention discloses an instruction branch prediction method and system. After the current instruction is executed, a preset number of instructions to be executed in the sequential execution direction are obtained and cached, and it is judged whether the first cached instruction is a jump instruction type. If If it is, calculate the jump target address and cache the target jump instruction. When the jump condition is met, it directly reads the cache of the target jump instruction to execute the jump instruction. If the jump condition cannot be met, it directly reads the cache for sequential execution. The second instruction in the direction, when the jump instruction is executed, no matter whether the jump condition is met or not, the subsequent instructions to be executed have been obtained and can be directly read from the cache for execution, through jump instruction prediction, instruction prefetch, instruction The mode of cache and direct read cache realizes bidirectional instruction branch prediction, solves the processor pipeline stall caused by jump instructions, and eliminates the reduction in processor execution efficiency caused by inserting branch delay gaps.