The invention belongs to the technical field of reconfigurable computing, particularly relates to an array processor under a dual-mode instruction set architecture, which can avoid loaduse adventure pause, and aims at solving the problem that when an existing traditional instruction set architecture faces loaduse-use adventure, the problem must be solved by a method of pausing an assembly line, and provides the following scheme that the array processor comprises an array processor body, the array processor body comprises a global controller, a processing element array, an instruction memory and a data memory, the instruction memory is connected with the global controller, the global controller is connected with the processing element array, and the processing element array is connected with the data memory. According to the array processor, a traditional branch delay slot design is not adopted, and assembly line pause or assembly line scouring cannot be generated for any existing risk, so that the design of a hardware circuit is greatly simplified, area resources are saved, the power consumption of the array processor is reduced, and the performance of the array processor is improved.