5 results about "Threaded code" patented technology

Code running on a processing unit can retain a hold on an active thread thereby preventing another thread running on the processing unit from executing. This can occur when the code requests more threads to be executed than the processing unit can give forward progress to, e.g., more threads than can be run simultaneously. Inserting the conventional yield instruction can lead to processing inefficiency such that the yield instruction can be executed more times than necessary thereby leading to an inefficiency in processing cycles of the processing unit performing the thread-switching routines. A yield occasionally instruction can be inserted into the code instead of the yield instruction. The yield occasionally can limit the times a yield instruction is executed thereby improving the efficiency of the processing cycles. The yield occasionally instruction can be used in non-terminating regions of the code, where the forward progress of other threads cannot be guaranteed.

The invention relates to a multi-thread parallel redundancy fault-tolerant method based on a compilation layer. The invention relates to the technical field of embedded processor design. The method comprises the following steps: determining thread division and an SoR region core; packaging an SoR region related fault-tolerant function library, packaging a core fault-tolerant function into a header file, and ensuring that a library file contains a tool function strongly associated with the SoR region; matching the compiler with the tool chain; marking and automatically identifying the source program; automatically identifying and supplementing the ROSE compiler; compiling the SoR region and generating a dual-thread code; performing double-thread parallel execution and check point interaction; and redundant fault-tolerant processing and flow continuation are carried out. The method does not depend on a specific hardware platform, and the problem of poor portability of a traditional hardware redundancy technology or a fault-tolerant technology depending on a specific hardware architecture is effectively avoided.

The application relates to a system test method, device, equipment, storage medium and program product. The method comprises the following steps: obtaining at least one service request for a target system to be tested; determining thread code coverage data of thread code processing the service request in the target system for each service request, and mapping interface identification information obtained by analyzing the service request to the thread code coverage data to obtain mapping data of the service request; merging the mapping data of the at least one service request respectively to obtain a mapping knowledge base of the target system; obtaining code difference information of the target system and a historical version system of the target system; querying interface identification information influenced by system version change from the mapping knowledge base based on the code difference information; and the interface identification information obtained by the querying is used for positioning a test range of the target system. The system test efficiency can be improved by using the method.

The embodiment of the invention provides a thread-based scheduling method, which comprises the following steps of: acquiring a loop instance of a target thread, and identifying loop content running in the loop instance and a pause statement in the loop content; splitting the loop content according to the pause statement to generate at least one event instance for independent operation; and querying critical zone resources accessed by the event instances, grouping the event instances according to the queried critical zone resources, and carrying out parallel scheduling on the grouped event instances. Therefore, thread parallelization is achieved, thread codes do not need to be modified, the problem that the parallel thread number cannot be automatically adjusted to adapt to different concurrent processes in the mode of modifying source codes to achieve thread parallelization scheduling in the prior art is solved, the thread parallelization performance and the system utilization efficiency are fully improved, and the thread parallelization scheduling method and device are easy to implement. And the modeling time is greatly reduced.

The invention discloses a CPU core binding method and device for cross-process operation, equipment and a storage medium, an eBPF code segment is inserted in an IPC driver, the IPC driver responds to an IPC operation request to determine a thread ID of a target thread, the eBPF code segment returns the thread ID to a service process before the target thread is awakened, the service process binds the target thread to a target CPU core based on the thread ID, and the target CPU core binds the target thread to the target CPU core based on the target CPU core. According to the method and the device, the IPC operation request is responded on the target CPU core, a user does not need to register a target process ID, a register does not need to be monitored to capture the process ID, and the target process does not need to be pre-judged through a complex algorithm, so that the target thread needing to be awakened by the IPC drive in the kernel is identified through the inserted eBPF code segment to perform the core binding operation during cross-process core binding operation; the method is suitable for CPUs of various architectures, the compatibility is good, the algorithm is simple, the accurate thread ID can be obtained, a user does not need to obtain the thread ID, and the user friendliness is improved.