Debugging multithreaded code

Abstract

Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with the hardware unit is searched for an entry in the CAM corresponding to the target memory address. In response to an entry in the CAM corresponding to the target memory address being found, a determination is made as to whether information in the entry identifies the instruction as an instruction of interest. In response to the entry identifying the instruction as an instruction of interest, an exception is generated and sent to one of an exception handler or a debugger application. In this way, debugging of multithreaded applications may be performed in an efficient manner.

Description

Background technique [0001] The present application relates generally to improved data processing apparatus and methods, and more particularly to mechanisms providing support for debugging multi-threaded code. [0002] In the current state of the art, writing computer programs to run in multiple threads is an accepted method for improving application performance. Unlike single-threaded applications, which execute instructions sequentially in program order, multithreaded applications improve performance by running multiple threads simultaneously on the various processing components of the system. Performance is improved because multiple processors or hardware threads often run multithreaded code, helping applications complete their tasks in less time. [0003] However, development of multithreaded applications remains a difficult task because programmers often have to insert synchronization code to make threads behave in the desired manner in order to compute equivalent result...

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