System and method for hiding memory latency

Abstract

A System and method for hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and / or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound.

Description

BACKGROUND OF THE INVENTION

[0001] 1. Technical Field

[0002] The present invention relates in general to a system and method for hiding memory latency. More particularly, the present invention relates to a system and method for, in a multi-thread environment, passing control from a first thread to a second thread when the first thread encounters a prolonged instruction.

[0003] 2. Description of the Related Art

[0004] Developers attempt to increase a computer system's performance by improving both the hardware aspects and the software aspects of the computer system. From a hardware perspective, a hardware developer may focus on improving areas such as a microprocessor's speed, bus interface speed, and memory size. From a software perspective, a developer may design an application to invoke multiple threads in order to increase the application's performance. For example, a gaming application may invoke a thread to render terrain data for the left half of a computer screen, and invoke ...

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