3results about How to "Increase computing density" patented technology

This invention relates to the field of chip design technology, and in particular to a dedicated interconnect device integrated within a graphics processor. The device includes a dedicated transmission channel comprising a dedicated data format conversion module, a verification and packaging module, and an alignment and allocation module cascaded in sequence, forming a unified transmission and reception path. In the transmission path, data flows sequentially through the dedicated data format conversion module, the verification and packaging module, and the alignment and allocation module. In the reception path, data flows sequentially through the alignment and allocation module, the verification and packaging module, and the dedicated data format conversion module. This dedicated interconnect device can be used for chip-to-chip communication outside of a package, as well as for direct die-to-die connections within an advanced package. It possesses good scalability and versatility, achieving low-latency, high-bandwidth communication.

This invention discloses a recurrent neural network physical architecture based on artificial surface plasmon supercells, relating to the interdisciplinary fields of metamaterials, surface plasmons, and brain-like computing. The architecture consists of multiple identical planar network layers stacked sequentially in the vertical direction. Each layer includes a dielectric substrate (1), an SSPP supercell array (2), a bi-line divider (3), and a combiner (4). The SSPP supercell array is connected to inter-layer feedback links via vias. Its output is divided into an output path and a feedback path by a bi-line divider. The feedback path integrates an RF amplifier (5) for gain compensation and transmits the signal across layers to the combiner in the next layer for vector superposition with the new input signal. This architecture integrates temporal feature extraction, nonlinear modulation, and recursive computation, possessing ultra-high-speed parallel processing capabilities, and can effectively realize deep fusion and associative decision-making of multimodal information based on the nonlinear coherence effect of SSPP waves.

This invention discloses a block pruning method for convolutional neural networks based on FPGA, comprising the following steps: training the network or using a pre-trained network and recording the network accuracy; grouping continuous weights into blocks of a predetermined size and determining the average value of each block; iteratively pruning from the block with the lowest average value according to a pruning percentage p; recording the accuracy of the pruned network, and when the difference between the accuracy of the original network and the accuracy of the pruned network is less than a threshold, iteratively increasing the pruning percentage p and continuing pruning; after determining a suitable pruning percentage p, performing 8-bit quantization on the data; fine-tuning the network, outputting the network parameters, and performing image recognition through the neural network. The method of this invention has a simple calculation process and high inference performance.