6results about How to "Increase computing density" patented technology

The invention belongs to the technical field of model training, and particularly relates to a large model increment training method and system based on dynamic sparsification. The method comprises the following steps: S1, evaluating the parameter importance of a large model by adopting a multi-dimensional evaluation method, and reflecting the contribution of parameters to the performance of the large model; s2, performing dynamic sparsification control on the large model structure by adopting a self-adaptive structure adjustment method; s3, performing incremental training management on the large model by constructing a capacity-adjustable empirical playback buffer pool and proposing a multi-objective loss function; and S4, carrying out model compression optimization on the large model by adopting a mixed precision quantification strategy. The method has the characteristics that the network structure can be dynamically adjusted by evaluating the importance of model parameters in real time, so that the efficient training is realized while the model performance is ensured.

The invention discloses a multilayer convolution operator fusion optimization method and device, equipment, a medium and a product, and relates to the technical field of compilation optimization, and the method comprises the steps: determining an original calculation graph of a to-be-deployed model, and determining a plurality of fusible operator sub-graphs in the original calculation graph based on a hardware performance model; optimizing the original calculation graph based on the fusible operator sub-graph to obtain an optimized calculation graph; obtaining a parallel optimization code of the to-be-deployed model based on the optimization calculation graph and the fragment size; the target machine runs the parallel optimization code to obtain the optimization performance of the to-be-deployed model; according to the method, the original calculation graph is optimized based on the fusible operator sub-graph, so that the performance of the target machine during execution of the neural network model can be improved.

The invention relates to an image edge detection method based on a memristor array ant colony algorithm, and belongs to the technical field of image processing and computer vision. The memristor has the characteristics of programmability, non-volatility and high-density arrangement, and fusion of storage and calculation can be realized. And each ant selects an optimal path for edge search in the image according to the pixel contrast as a heuristic factor. Through the memristor array, parallel path selection and pheromone updating of the ant colony optimization algorithm are realized, a plurality of pixel points of the image can be processed at the same time, and the calculation efficiency is greatly improved. According to the invention, large-scale path selection and updating are carried out by using the parallel computing capability of memristor elements through a cross array structure. According to the method, finer image edges can be detected, and meanwhile, the method has remarkable advantages in the aspects of calculation speed and energy consumption. The method can be applied to the fields of image processing, mode recognition and artificial intelligence, and has high practical value and wide application prospect.

This invention relates to the field of chip design technology, and in particular to a dedicated interconnect device integrated within a graphics processor. The device includes a dedicated transmission channel comprising a dedicated data format conversion module, a verification and packaging module, and an alignment and allocation module cascaded in sequence, forming a unified transmission and reception path. In the transmission path, data flows sequentially through the dedicated data format conversion module, the verification and packaging module, and the alignment and allocation module. In the reception path, data flows sequentially through the alignment and allocation module, the verification and packaging module, and the dedicated data format conversion module. This dedicated interconnect device can be used for chip-to-chip communication outside of a package, as well as for direct die-to-die connections within an advanced package. It possesses good scalability and versatility, achieving low-latency, high-bandwidth communication.

This invention discloses a recurrent neural network physical architecture based on artificial surface plasmon supercells, relating to the interdisciplinary fields of metamaterials, surface plasmons, and brain-like computing. The architecture consists of multiple identical planar network layers stacked sequentially in the vertical direction. Each layer includes a dielectric substrate (1), an SSPP supercell array (2), a bi-line divider (3), and a combiner (4). The SSPP supercell array is connected to inter-layer feedback links via vias. Its output is divided into an output path and a feedback path by a bi-line divider. The feedback path integrates an RF amplifier (5) for gain compensation and transmits the signal across layers to the combiner in the next layer for vector superposition with the new input signal. This architecture integrates temporal feature extraction, nonlinear modulation, and recursive computation, possessing ultra-high-speed parallel processing capabilities, and can effectively realize deep fusion and associative decision-making of multimodal information based on the nonlinear coherence effect of SSPP waves.

This invention discloses a block pruning method for convolutional neural networks based on FPGA, comprising the following steps: training the network or using a pre-trained network and recording the network accuracy; grouping continuous weights into blocks of a predetermined size and determining the average value of each block; iteratively pruning from the block with the lowest average value according to a pruning percentage p; recording the accuracy of the pruned network, and when the difference between the accuracy of the original network and the accuracy of the pruned network is less than a threshold, iteratively increasing the pruning percentage p and continuing pruning; after determining a suitable pruning percentage p, performing 8-bit quantization on the data; fine-tuning the network, outputting the network parameters, and performing image recognition through the neural network. The method of this invention has a simple calculation process and high inference performance.