System and method for processing jump instruction of microprocessor in branch prediction way

Abstract

The invention discloses a system and a method for processing a jump instruction of a microprocessor in a branch prediction way. The system comprises a coding module and a transmission module, wherein the coding module comprises a branch predictor used for predicting by adopting a static prediction method when the jump instruction to be processed is in the jump execution type or adopting a dynamic prediction method when the jump instruction to be processed is not in the jump execution type after the coding module judges that an instruction to be processed is the jump instruction and judges the type of the jump instruction through precoding, and directly writing the jump instruction to be processed and a delay slot instruction thereof in an operational queue in a sequence of the instructions in a program; and the transmission module comprises a prediction result processor used for canceling the instruction executed by error and continue fetching in a correct jump direction when the branch predictor predicts the jump instruction by error after the jump instruction is executed and written back to the transmission module. The system cancels operation by adopting different cancellation methods on the basis that whether the instruction is the jump execution instruction or not when the instruction is cancelled.

Description

technical field [0001] The invention relates to the field of microprocessor architecture, in particular to a microprocessor jump instruction branch prediction processing system and method. Background technique [0002] In the existing microprocessor system, the jump instruction brings many challenges to the design of the microprocessor. For example, for a microprocessor with a pipeline structure, when the microprocessor is executing a program with a jump instruction, if it encounters a jump instruction, it is possible to determine whether the jump instruction jumps and the address of the jump target at the earliest. The pipeline stage is a decoding stage, such as a direct jump (jump) instruction. [0003] However, for most jump instructions, the jump direction and jump target address of the jump instruction cannot be determined until the execution stage is completed. At this time, the subsequent instructions may have been fetched from the memory, and what is more, they hav...

AI Technical Summary

Problems solved by technology

[0010] Since jump instructions cannot be used as delay slot instructions, any other type of instruction can be used as a delay slot instruction, so positioning the delay slot instruction and deciding whether to cancel the delay slot instruction according to the jump instruction corresponding to the delay slot instruction makes the present Some branch prediction methods are more complicated, and the existing branch prediction methods are not suitable for microprocessors with a superscalar processor structure, especially for microprocessors with a MIPS structure.

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