Array processor capable of avoiding loaduse risk pause under dual-mode instruction set architecture

Abstract

The invention belongs to the technical field of reconfigurable computing, particularly relates to an array processor under a dual-mode instruction set architecture, which can avoid loaduse adventure pause, and aims at solving the problem that when an existing traditional instruction set architecture faces loaduse-use adventure, the problem must be solved by a method of pausing an assembly line, and provides the following scheme that the array processor comprises an array processor body, the array processor body comprises a global controller, a processing element array, an instruction memory and a data memory, the instruction memory is connected with the global controller, the global controller is connected with the processing element array, and the processing element array is connected with the data memory. According to the array processor, a traditional branch delay slot design is not adopted, and assembly line pause or assembly line scouring cannot be generated for any existing risk, so that the design of a hardware circuit is greatly simplified, area resources are saved, the power consumption of the array processor is reduced, and the performance of the array processor is improved.

Description

technical field [0001] The invention relates to the technical field of reconfigurable computing, in particular to an array processor under a dual-mode instruction set architecture that can avoid load_use risky pauses. Background technique [0002] There is a load-use risk in the pipeline processor designed under the traditional instruction set architecture, that is, the previous instruction is a load instruction, and the next instruction needs to read the data loaded from the data memory into the register by the previous load instruction. , In a pipeline processor designed under the traditional instruction set architecture, the data bypass method similar to the above will fail, and such a risk must be solved by the method of stalling the pipeline. [0003] When facing the load-use risk of traditional instruction set architecture, it must be solved by suspending the pipeline. SUMMARY OF THE INVENTION [0004] The purpose of the present invention is to solve the disadvantag...

AI Technical Summary

Problems solved by technology

[0002] There is a load-use risk in the pipeline processor designed under the traditional instruction set architecture, that is, the previous instruction is a load instruction, and the next instruction needs to read the data loaded from the data memory to the register by the previous load instruction. , in a pipelined processor designed under the traditional instruction set architecture, the data bypass method similar to the above will fail, and such hazards must be solved by stalling the pipeline

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