Array processor capable of avoiding loaduse risk pause under dual-mode instruction set architecture

An array processor and instruction set architecture technology, applied in the field of array processors, can solve problems such as the failure of data bypass methods, and achieve the effects of simplifying design, improving performance, and reducing power consumption

Pending Publication Date: 2022-04-08
XIAN UNIV OF POSTS & TELECOMM
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

[0002] There is a load-use risk in the pipeline processor designed under the traditional instruction set architecture, that is, the previous instruction is a load instruction, and the next instruction needs to read the data loaded from the data memory

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  • Array processor capable of avoiding loaduse risk pause under dual-mode instruction set architecture
  • Array processor capable of avoiding loaduse risk pause under dual-mode instruction set architecture
  • Array processor capable of avoiding loaduse risk pause under dual-mode instruction set architecture

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Embodiment Construction

[0021] The technical solutions in this embodiment will be clearly and completely described below with reference to the accompanying drawings in this embodiment. Obviously, the described embodiments are only a part of the embodiments of this embodiment, but not all of the embodiments.

[0022] refer to Figure 1-3 , the array processor under the dual-mode instruction set architecture can avoid the load_use risky pause, including the array processor body, which includes the global controller GLC, the processing element array PE_ARRAY, the instruction memory IM, the data memory DM, the instruction memory IM and the The global controller GLC is connected, the global controller GLC is connected with the processing element array PE_ARRAY, and the processing element array PE_ARRAY is connected with the data memory DM.

[0023] Among them, "dual mode" means that the instructions in the instruction set are divided into functional instructions for realizing control flow and operation in...

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Abstract

The invention belongs to the technical field of reconfigurable computing, particularly relates to an array processor under a dual-mode instruction set architecture, which can avoid loaduse adventure pause, and aims at solving the problem that when an existing traditional instruction set architecture faces loaduse-use adventure, the problem must be solved by a method of pausing an assembly line, and provides the following scheme that the array processor comprises an array processor body, the array processor body comprises a global controller, a processing element array, an instruction memory and a data memory, the instruction memory is connected with the global controller, the global controller is connected with the processing element array, and the processing element array is connected with the data memory. According to the array processor, a traditional branch delay slot design is not adopted, and assembly line pause or assembly line scouring cannot be generated for any existing risk, so that the design of a hardware circuit is greatly simplified, area resources are saved, the power consumption of the array processor is reduced, and the performance of the array processor is improved.

Description

technical field [0001] The invention relates to the technical field of reconfigurable computing, in particular to an array processor under a dual-mode instruction set architecture that can avoid load_use risky pauses. Background technique [0002] There is a load-use risk in the pipeline processor designed under the traditional instruction set architecture, that is, the previous instruction is a load instruction, and the next instruction needs to read the data loaded from the data memory into the register by the previous load instruction. , In a pipeline processor designed under the traditional instruction set architecture, the data bypass method similar to the above will fail, and such a risk must be solved by the method of stalling the pipeline. [0003] When facing the load-use risk of traditional instruction set architecture, it must be solved by suspending the pipeline. SUMMARY OF THE INVENTION [0004] The purpose of the present invention is to solve the disadvantag...

Claims

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Application Information

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IPC IPC(8): G06F9/38
Inventor 刘有耀韩思懿王禹舜李隆一张奇龙王昊驰
Owner XIAN UNIV OF POSTS & TELECOMM
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