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Method and apparatus for jump delay slot control in pipelined processor

A digital processor and processor technology, applied in the direction of electrical digital data processing, machine execution devices, special data processing applications, etc., can solve the problems of increasing the complexity of basic codes and increasing the efficiency of pipelines, etc.

Inactive Publication Date: 2005-08-31
SYNOPSYS INC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Compared to the multi-cycle transfer described above, this approach increases the efficiency of the pipeline, but also increases the complexity of the basic code (easy for programmers to understand)

Method used

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  • Method and apparatus for jump delay slot control in pipelined processor
  • Method and apparatus for jump delay slot control in pipelined processor
  • Method and apparatus for jump delay slot control in pipelined processor

Examples

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no. 1 example

[0072] As shown in Table 1, all 64 registers (ie r0-r63) are specified. The first set of 32 registers (r0-r31) are general-purpose registers used to reflect register values. The next 28 registers (r32-r59) are extended registers that specify special applications. The next register (r60) is the loop count register which is used in part in the ARC processor as a zero-overhead loop mechanism to maintain a count of repetition numbers kept in a loop structure. Use the last three registers (r61-r64) to represent an immediate operand data (shimmf, limm or shimm, respectively). Since the bits in the instruction word used to set the flags are required to encode the short immediate data, there are two versions of the shimm; one with the sign set (i.e. shimmf) and one without the sign set (i.e. shimm). Figures 3a-3c illustrate the above-mentioned register encoding structure according to the present invention

[0073] Example.

[0074] The above method gives the programmer / desi...

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Abstract

A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating 'makefiles' for purposes of simulation and / or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Description

[0001] This patent application is a divisional application. The application number of the parent case is 00808462.9, and the application date is May 12, 2000. The parent application is a PCT application entering China, and the application number of the PCT application is PCT / US00 / 13198. The international filing date is May 12, 2000. technical field [0002] This invention relates to the design of digital processors, and more particularly to the design of user-customized processors. Background technique [0003] RISC (Reduced Instruction Set Computer) processors are well known in the computer arts. Compared with non-RISC (commonly referred to as "CISC") processors, RISC processors generally have the fundamental property of utilizing a substantially reduced instruction set. Typical RISC processor machine instructions are not all microcoded and can be executed immediately without decoding, thus providing meaningful economic benefits in processing speed. This "streamlined" in...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F9/318G06F9/38G06F17/50
CPCG06F9/30156G06F17/5045G06F9/30181G06F9/30145G06F9/3867G06F9/30167G06F9/30105G06F30/30
Inventor P·沃恩斯C·格林汉姆
Owner SYNOPSYS INC
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