A method and a device for generating a standard delay format file

Abstract

The invention provides a method and a device for generating a standard delay format file. The method comprises the following steps: according to a standard cell library and an input file used by a chip, carrying out time sequence analysis on the chip, and determining a standard cell of a time sequence violation; Replacing the standard unit of the time sequence violation with a virtual unit of thestandard unit of the time sequence violation meeting the Setup / Hold time sequence requirement to obtain a tcl format file for repairing the time sequence; According to the tcl format file, generatinga standard delay format file meeting a Setup / Hold time sequence requirement; And modifying the name of the virtual unit of the standard unit used for replacing the time sequence violation in the standard time delay format file into the name of the replaced standard unit of the time sequence violation to obtain a final standard time delay format file. According to the method, the SDF file meeting the Setup / Hold time sequence requirement at the early stage of back-end time sequence convergence can be generated under the condition that a netlist is not changed.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a method and a device for generating a standard delay format file. Background technique [0002] For ASIC chip design, it is necessary to output a Standard Delay Format (SDF) file during the timing convergence process of the chip backend. Through the post-simulation with the SDF file, possible constraint errors or design errors of the chip can be found. [0003] The SDF file is generated by the back-end timing convergence tool by reading in the Netlist netlist and SPEF parasitic parameters. The SDF file describes the delay of each cell / net in the design and the Setup / Hold check value of the timing unit. The post-simulation tool reads in After the SDF file is reversed, it can output waveforms and working environments that are close to the real one, so as to finally verify whether the chip can work correctly. [0004] However, in the design process, the time to provide the SDF...

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Problems solved by technology

[0004] However, in the design process, the time to provide the SDF file that meets the Setup / Hold timing requirements is generally relatively late. After the post-simulation with SDF finds a problem, the time for modification will be relatively short. Therefore, how to do it in the early stage of back-end timing convergence It is necessary to generate an SDF file that meets the Setup / Hold timing requirements at the same time

[0005] At present, the commonly used method in the industry is set_annotated_delay. By adding an additional annotated_delay, it can only meet the Hold timing requirements, but not the Setup timing requirements. For the Setup timing, post-simulation needs to reduce the frequency to avoid timing violations and complete the simulation.

The problem of frequency reduction is also obvious. For some real problems, it may not be verified due to frequency reduction, so the existing methods have great limitations.

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