Novel CSD constant multiplier algorithm structure for 256-point FFT processor

A technology of algorithm structure and multiplier, which is applied in complex mathematical operations, electrical digital data processing, special data processing applications, etc., can solve the problems of low hardware cost and complex structure of CSD constant multiplier, and achieve good power consumption and save calculation Time, reduce the effect of hardware investment

Inactive Publication Date: 2019-08-16
HEBEI NORMAL UNIV FOR NATTIES
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Problems solved by technology

However, when the number of FFT processor points exceeds 64 points, the structure of the CSD constant multiplier becomes extremely complicated, and there is no advantage in hardware costs compared to the Booth multiplier.

Method used

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  • Novel CSD constant multiplier algorithm structure for 256-point FFT processor
  • Novel CSD constant multiplier algorithm structure for 256-point FFT processor
  • Novel CSD constant multiplier algorithm structure for 256-point FFT processor

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Embodiment Construction

[0020] The present invention provides a novel cascaded CSD constant multiplier algorithm structure for a 256-point FFT processor, the algorithm structure comprising the following steps:

[0021] Step 1, using symmetry to change the number of twiddle factor constant values ​​from 256 to the original 1 / 8 or 36, and the twiddle factor is represented by the following formula:

[0022]

[0023] like image 3 As shown, the symmetric map is equally divided into A-H8 areas, and N in the figure is the number of FFT points, where the real part of the A area is expressed as x p , the imaginary part is denoted as y p , the constant denoted as x p +jy p ; The real part of the B area is expressed as -y p , the imaginary part is expressed as -x p , the constant is expressed as -y p -jx p ; The real part of the region C is denoted as y p , the imaginary part is expressed as -x p , the constant denoted as y p -jx p ; The real part of the D area is expressed as -x p , the imagina...

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Abstract

The invention provides a novel CSD constant multiplier algorithm structure for a 256-point FFT processor. The novel CSD constant multiplier algorithm structure comprises the following steps that 1, changing the number of constant values of a rotation factor into 1 / 8 of the original number through symmetry; 2, decomposing the coefficient of the rotation factor into two coefficients by adopting a parameter decomposition method; and step 3, performing CSD representation on the rotation factor constant value in the value range of the coefficient decomposed in the step 2, and performing drawing according to the CSD representation to realize a 256-point FFT complex multiplication operation mode by utilizing the proposed novel CSD constant multiplier connected in series. According to the invention, the hardware resource cost of the designed 256-point FFT processor can be greatly reduced, the power consumption can be well controlled, and the requirements of different industrial occasions can be better met.

Description

technical field [0001] The invention relates to the technical field of ultra-large-scale integrated circuit design, in particular to a novel cascaded CSD constant multiplier algorithm structure for a 256-point FFT processor. Background technique [0002] In FFT processor design, when the number of FFT points exceeds 64 points, the multiplier used for complex multiplication is generally a Booth multiplier, which not only consumes high hardware resources but also requires an additional ROM to store the coefficients of the twiddle factors. The complex multiplication unit is a key module of the FFT processor, which consumes a lot of hardware costs. The Booth multiplier can halve the number of partial products in the multiplication process and is often used for complex multiplication in FFT processors. Compared with the Booth multiplier, the Canonical Signed Digit (CSD) constant multiplier consumes less hardware resources and does not require ROM to store the coefficients of the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14G06F7/533
CPCG06F17/142G06F7/5332
Inventor 于建顾建军姚宇凤
Owner HEBEI NORMAL UNIV FOR NATTIES
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