Data processor, method, chip and electronic equipment

A data processor and data technology, applied in the computer field, can solve the problem of high complexity of multiply-accumulate operations

Active Publication Date: 2019-11-05
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the traditional technology, the number of non-zero bit values ​​in the code is large, and the number of corresponding effective partial pro

Method used

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  • Data processor, method, chip and electronic equipment
  • Data processor, method, chip and electronic equipment
  • Data processor, method, chip and electronic equipment

Examples

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Embodiment Construction

[0075] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0076] The data processor provided by this application can be applied to AI chips, field-programmable gate array FPGA (Field-Programmable Gate Array, FPGA) chips, or other hardware circuit devices for multiplication processing or multiplication-accumulation processing. The structure diagram of the processor is shown in the figure 1 with 2 shown.

[0077] Such as figure 1 as shown, figure 1 A structural diagram of a data processor provided for an embodiment. Such as figure 1 As shown, the data processor includes: a first multiplication circuit 11, a second multiplicat...

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Abstract

The invention provides a data processor, a method, a chip and electronic equipment. The data processor comprises a first multiplication circuit, a second multiplication circuit and a partial product switching circuit. The first multiplication circuit comprises a first correction coding sub-circuit and a first correction compression sub-circuit. The second multiplication operation circuit comprisesa second correction coding sub-circuit and a second correction compression sub-circuit. The data processor can perform regular symbolic number coding processing on the received data, so that the number of obtained effective partial products is relatively small. The complexity of realizing multiplication operation or multiply-accumulate operation by the data processor is reduced.

Description

technical field [0001] The present application relates to the field of computer technology, in particular to a data processor, method, chip and electronic equipment. Background technique [0002] With the continuous development of digital electronic technology, the rapid development of various artificial intelligence (AI) chips has higher and higher requirements for high-performance data processors. Among them, the data processor is a multiplier, an adder or a multiplier accumulator. The neural network algorithm is one of the algorithms widely used in smart chips, and multiply-accumulate operation through the multiply-accumulator is a common operation in the neural network algorithm. [0003] At present, the data processor uses every three-digit value in the multiplier as a code, and obtains partial products according to the multiplicand, and uses a Wallace tree to compress all partial products to obtain multiplication results or multiplication-accumulation results. Howeve...

Claims

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Application Information

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IPC IPC(8): G06F7/50G06F7/52G06F9/30G06N3/063
CPCG06F7/50G06F7/52G06F9/30007G06N3/063Y02D10/00
Inventor 不公告发明人
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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