Time schedule controller
A timing controller and display technology, applied in digital video signal modification, electrical components, image communication, etc.
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[0031] figure 1 A block diagram of a display 100 according to an embodiment of the present invention is shown. In this embodiment, a display 100 (such as a liquid crystal display) may include a panel 11 , a scan driver 12 , a data driver 13 and a timing controller (T-con) 14 . Wherein, the panel 11 includes a plurality of pixels (not shown) arranged in a matrix. The scan driver 12 is controlled by the timing controller 14 to sequentially activate the corresponding columns of pixels of the control panel 11 through the plurality of scan lines 121 . The data driver 13 is controlled by the timing controller 14 and receives the image signal, and transmits the image signal to the pixels of the corresponding row (or channel) of the panel 11 through the plurality of data lines 131 . The timing controller 14 includes an encoder 141, which uses a downsampling method for data compression of the video signal.
[0032] figure 2 Shows a simplified example of downsampling, where data 1,...
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